Patents by Inventor Wen-Yu Ho

Wen-Yu Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957722
    Abstract: The present invention discloses an anti-aging composition, which includes: (a) isolated lactic acid bacterial strains or a fermented product thereof; and (b) an excipient, a diluent, or a carrier; wherein the isolated lactic acid bacterial strains include: Bifidobacterium bifidum VDD088 strains, Bifidobacterium breve Bv-889 strains, and Bifidobacterium longum BLI-02 strains. The present invention further provides a method for preventing aging by administering the foregoing anti-aging composition to a subject in need thereof.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 16, 2024
    Assignee: GLAC BIOTECH CO., LTD
    Inventors: Hsieh-Hsun Ho, Yi-Wei Kuo, Wen-Yang Lin, Jia-Hung Lin, Yen-Yu Huang, Chi-Huei Lin, Shin-Yu Tsai
  • Patent number: 11911421
    Abstract: Disclosed herein is a probiotic composition that includes Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9, which are deposited at the China Center for Type Culture Collection (CCTCC) respectively under accession numbers CCTCC M 2011127, CCTCC M 2011128, and CCTCC M 2014588. A number ratio of Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9 ranges from 1:0.1:0.1 to 1:1:8. Also disclosed herein is use of the probiotic composition for alleviating type 1 diabetes mellitus (T1DM).
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 27, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Wen-Yang Lin, Yi-Wei Kuo, Yen-Yu Huang, Jia-Hung Lin
  • Patent number: 7772625
    Abstract: A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein the RPO layer has a level of nitrogen of about 0.35 atomic % or less.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: August 10, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao Hsiang Liang, Wen-Kung Cheng, Chen-Peng Fan, Ming-Hsien Chen, Richard Chen, Jung-Chen Yang, Wen-Yu Ho, Chao-Keng Li, Yong-Sin Chang, Labo Chang
  • Publication number: 20080083938
    Abstract: A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein the RPO layer has a level of nitrogen of about 0.35 atomic % or less.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 10, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao Hsiang Liang, Wen-Kung Cheng, Chen-Peng Fan, Ming-Hsien Chen, Richard Chen, Jung-Chen Yang, Wen-Yu Ho, Chao-Keng Li, Yong-Sin Chang, Labo Chang
  • Publication number: 20040224501
    Abstract: A method of making tungsten plug of integrated circuit is disclosed. The present invention is structured to deposit W metal by CVD onto the wafer which has Ti/TiN sputtered on as its top layer by employing quartz clamp rings of different sizes in two CVD chambers. The method can eliminate the Volcano phenomena in Ti, TiN or W metals and prevent peeling.
    Type: Application
    Filed: February 8, 2002
    Publication date: November 11, 2004
    Inventors: YUNG-TSUN LO, RAYMOND TSAI, WEN-YU HO
  • Patent number: 6228753
    Abstract: A method of fabricating bonding pad structure for improving bonding pad surface quality. A substrate has a bonding pad thereon. A passivation is formed on the bonding pad to expose the bonding pad. A sacrificial layer is formed on the passivation and an opening is formed within the sacrificial layer to expose the bonding pad. A Cu/Al alloy is formed on the passivation to at least cover the bonding pad. The sacrificial layer and the Cu/Al alloy thereon are removed, such that the Cu/Al alloy remains on the bonding pad.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: May 8, 2001
    Assignee: Worldwide Semiconductor Mfg Corp
    Inventors: Yung-Tsun Lo, Wen-Yu Ho, Sung-Chun Hsieh
  • Patent number: 6096645
    Abstract: A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably between approximately 32 s and 52 s) to reduce the tendency of the resistance and thickness of the as-deposited film to change because of either time of exposure to atmosphere or subsequent processing steps.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 1, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Yung-Tsun Lo, Hui-lun Chen, Wen-Yu Ho, Sung-chun Hsieh, Feng-hsien Chao
  • Patent number: 6030893
    Abstract: The present invention is a chemical vapor deposition of tungsten(W-CVD)process for growing low stress and void free interconnect. The method of this invention utilizes two steps W-CVD process by two chambers. The first step, filling tungsten metal completely in the contact hole, is performed in the first chamber. The second step, forming a tungsten layer for interconnect, is performed in the second chamber. Because of using two different chambers, the method of this invention can adjust the temperature of the process and the gas flow of the WF.sub.6 vapor of the process for different required the two steps. The second step of chemical vapor deposition of tungsten by adjusting the temperature and the gas flow has reduced greatly the stress of the second conductive layer. Moreover, the first step of chemical vapor deposition of tungsten by adjusting the temperature and the gas flow prevents voids in the contact hole or in the via hole.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: February 29, 2000
    Assignee: Mosel Vitelic Inc.
    Inventors: Yung-Tsun Lo, Cheng-Hsun Tsai, Wen-Yu Ho, Sung-Chung Hsieh
  • Patent number: 6022800
    Abstract: A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention provides a barrier layer prepared by first forming a conformal layer of titanium nitride by chemical vapor deposition. Afterward, another film of titanium nitride is supplied by plasma vapor deposition. The barrier layer comprises at least these two films, and tungsten is then deposited to at least fill the high aspect ratio film-coated contact hole. Upon removal of excess tungsten as by wet etch back, the tungsten plug remains essentially intact, and any plug loss is insignificant in comparison with the prior art.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: February 8, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corporation
    Inventors: Wen-Yu Ho, Sen-Nan Lee, Sung Chun Hsieh, Hui-Lun Chen
  • Patent number: 5966626
    Abstract: The present invention provides a method for stabilizing the crystal structure of a silicon substrate after an ion implantation process including the step of exposing the substrate to a temperature not higher than 200.degree. C. for a time period of not less than 10 seconds, and preferably to a temperature between about 100.degree. C. and about 200.degree. C. for a time period of between about 10 seconds and about 10,000 seconds.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: October 12, 1999
    Assignee: Mosel Vitelic, Inc.
    Inventors: Yung-Tsun Lo, Cheng-Hsun Tsai, Wen-Yu Ho, Jung-Chun Hsieh