Patents by Inventor Wen-Yun Wang
Wen-Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11931456Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.Type: GrantFiled: November 16, 2022Date of Patent: March 19, 2024Assignee: MegaPro Biomedical Co. Ltd.Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang
-
Publication number: 20240071830Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature, gate lines, and a first gate structure. The isolation feature is over the semiconductor substrate and surrounding an active region of the semiconductor substrate. The gate lines extend across the active region of the semiconductor substrate. The first gate structure is over the isolation feature. The first gate structure comprises a first gate line, a second gate line, and a first bridge portion, the first and second gate lines are substantially parallel with the gate lines, and the first bridge portion connects the first gate line to the second gate line.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu LIU, Chia-He LIN, Wen-Yun WANG
-
Patent number: 11854854Abstract: A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.Type: GrantFiled: July 23, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Jen Chen, Wen-Yun Wang, Yen-Chun Chen, Po-Ting Yeh
-
Publication number: 20230049938Abstract: A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Yu-Fan Peng, Yuan-Ching Peng, Yu-Bey Wu, Yu-Shan Lu, Hung Yu Lai, Chen-Yu Chen, Wen-Yun Wang, Tang Ming Lee
-
Publication number: 20230024673Abstract: A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Inventors: Chang-Jen CHEN, Wen-Yun WANG, Yen-Chun CHEN, Po-Ting YEH
-
Publication number: 20220328304Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.Type: ApplicationFiled: July 8, 2021Publication date: October 13, 2022Inventors: Kuo-Chang Kau, Wen-Yun Wang, Chia-Chu Liu, Hua-Tai Lin
-
Patent number: 11392045Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: December 7, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
-
Publication number: 20210088915Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
-
Patent number: 10859924Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: April 27, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
-
Publication number: 20190146357Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: ApplicationFiled: April 27, 2018Publication date: May 16, 2019Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
-
Patent number: 9728469Abstract: Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 ?m after creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.Type: GrantFiled: March 13, 2013Date of Patent: August 8, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Ching-Yu Chang
-
Publication number: 20160260623Abstract: A system for forming a coating comprises applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the first coating after planarizing the top surface. The first coating may be applied over the plurality of topographical features, and may be substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating. A solvent may be applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The first coating may have a planar surface prior to drying the first coating, and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: Wen-Yun Wang, Cheng-Han Wu, Yu-Chung Su, Ching-Yu Chang
-
Patent number: 9436086Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: GrantFiled: January 25, 2016Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
-
Publication number: 20160155632Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: ApplicationFiled: January 25, 2016Publication date: June 2, 2016Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
-
Patent number: 9349622Abstract: A method of forming a coating, comprises applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the first coating after planarizing the top surface. The first coating may be applied over the plurality of topographical features, and may be substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating. A solvent may be applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The first coating may have a planar surface prior to drying the first coating, and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.Type: GrantFiled: March 13, 2013Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Cheng-Han Wu, Yu-Chung Su, Ching-Yu Chang
-
Patent number: 9245751Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.Type: GrantFiled: October 17, 2013Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chung Su, Ching-Yu Chang, Wen-Yun Wang
-
Patent number: 9239520Abstract: A system and method for reducing defects in photoresist processing is provided. An embodiment comprises cleaning the photoresist after development using an alkaline environment. The alkaline environment may comprise a neutral solvent and an alkaline developer. The alkaline environment will modify the attraction between residue leftover from development and a surface of the photoresist such that the surfaces repel each other, making the removal of the residue easier. By removing more residue, there will be fewer defects in the photolithographic process.Type: GrantFiled: April 27, 2015Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Ching-Yu Chang
-
Patent number: 9110376Abstract: A system and method for photoresists is provided. In an embodiment a photoresist is developed. Once developed, the photoresist is slimmed using either a direct slimming technique or an indirect slimming technique. In a direct slimming technique the slimming agent is either an alkaline solution or a polar solvent. In the indirect slimming technique a hydrophobic material is diffused into the photoresist to form a modified region and the modified region is then removed.Type: GrantFiled: March 15, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Cheng-Han Wu
-
Publication number: 20150227051Abstract: A system and method for reducing defects in photoresist processing is provided. An embodiment comprises cleaning the photoresist after development using an alkaline environment. The alkaline environment may comprise a neutral solvent and an alkaline developer. The alkaline environment will modify the attraction between residue leftover from development and a surface of the photoresist such that the surfaces repel each other, making the removal of the residue easier. By removing more residue, there will be fewer defects in the photolithographic process.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Wen-Yun Wang, Ching-Yu Chang
-
Patent number: 9017934Abstract: A system and method for reducing defects in photoresist processing is provided. An embodiment comprises cleaning the photoresist after development using an alkaline environment. The alkaline environment may comprise a neutral solvent and an alkaline developer. The alkaline environment will modify the attraction between residue leftover from development and a surface of the photoresist such that the surfaces repel each other, making the removal of the residue easier. By removing more residue, there will be fewer defects in the photolithographic process.Type: GrantFiled: March 8, 2013Date of Patent: April 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yun Wang, Ching-Yu Chang