Patents by Inventor Wenzhi Gao
Wenzhi Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12121476Abstract: An ophthalmic laser system and related method for forming a lenticular incision in a corneal lenticule extraction procedure. The lenticular incision is formed by multiple sweeps of a laser scan line along meridians of longitude of the lenticular incision, where the end point of each sweep is connected to the start point of the next sweep by a smooth turning trajectory. The trajectory includes a first circular arc tangentially connected to the first sweep at its end point, a second circular arc tangentially connected to the next sweep at its start point, and a straight line segment tangentially connected to both circular arcs. The smooth trajectory is determined with the given limits of velocity, acceleration and jerk of the XY scanning motors, without using high frequency filters to smooth the trajectory, thereby avoiding unknown changes to the original trajectory and achieving high precision lenticule shapes.Type: GrantFiled: April 6, 2022Date of Patent: October 22, 2024Assignee: AMO Development, LLCInventors: Wenzhi Gao, Hong Fu
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Publication number: 20240307229Abstract: An ophthalmic surgical laser system and method for forming a lenticule in a subject's eye using “fast-scan-slow-sweep” scanning scheme. A high frequency scanner forms a fast scanline, which is placed tangential to a parallel of latitude of the surface of the lenticule and then moved in a slow sweep trajectory along a meridian of longitude of the surface of the lenticule in one sweep. Multiple sweeps are performed along different meridians to form the entire lenticule surface, with the orientation of the scanline rotated between successive sweeps. To reduce acceleration and jerk in the XY stage motion, especially during transition from one sweep to the next, the sweeping speed profile is a sigmoid function.Type: ApplicationFiled: February 28, 2024Publication date: September 19, 2024Inventors: Wenzhi Gao, Hong Fu
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Publication number: 20240197532Abstract: A method implemented in an ophthalmic surgical laser system that employs a resonant scanner, scan line rotator, and XY- and Z-scanners, for forming a corneal flap in a patient's eye with improved bubble management during each step of the flap creation process. A pocket cut is formed first below bed level, followed by the bed connected to the pocket cut, then by a side cut extending from the bed to the anterior corneal surface. The pocket cut includes a pocket region located below the bed level and a ramp region connecting the pocket region to the bed. The bed is formed by a bed cut, including multiple overlapping parallel raster scan passes, and a ring cut. The side cut is formed by multiple side-cut layers at different depths which are joined together. All cuts are formed by scanning a laser scan line generated by the resonant scanner.Type: ApplicationFiled: December 19, 2023Publication date: June 20, 2024Inventors: Andrew Voorhees, Hong Fu, James Hill, Mohammad Saidur Rahaman, Wenzhi Gao, Brian Schwam, Paul Gray, Cynthia Villanueva, Deepali Mehta-Hurt, Jesse Nelson, Michal Laron
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Publication number: 20230320898Abstract: An ophthalmic laser system and related method for forming a lenticular incision in a corneal lenticule extraction procedure. The lenticular incision is formed by multiple sweeps of a laser scan line along meridians of longitude of the lenticular incision, where the end point of each sweep is connected to the start point of the next sweep by a smooth turning trajectory. The trajectory includes a first circular arc tangentially connected to the first sweep at its end point, a second circular arc tangentially connected to the next sweep at its start point, and a straight line segment tangentially connected to both circular arcs. The smooth trajectory is determined with the given limits of velocity, acceleration and jerk of the XY scanning motors, without using high frequency filters to smooth the trajectory, thereby avoiding unknown changes to the original trajectory and achieving high precision lenticule shapes.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Inventors: Wenzhi Gao, Hong Fu
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Patent number: 10967514Abstract: Mechanical condition monitoring of robots can be used to detect unexpected failure of robots. Data taken from a robot operation is processed and compared against a health baseline. Features extracted during the monitoring stage of robot operation are aligned with features extracted during the training stage in which the health baseline is established by projecting both onto a common subspace. A classifier which can include a distance assessment such as an L2-norm is used within the common subspace to assess the condition of the robot. Excursions of the distance assessment from a criteria indicate a failure or potential failure.Type: GrantFiled: August 22, 2018Date of Patent: April 6, 2021Assignee: ABB Schweiz AgInventors: Arash Mahyari, Nevroz Sen, Thomas Locher, Wenzhi Gao, Dan Dai, Said Zahrai
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Publication number: 20200061833Abstract: Mechanical condition monitoring of robots can be used to detect unexpected failure of robots. Data taken from a robot operation is processed and compared against a health baseline. Features extracted during the monitoring stage of robot operation are aligned with features extracted during the training stage in which the health baseline is established by projecting both onto a common subspace. A classifier which can include a distance assessment such as an L2-norm is used within the common subspace to assess the condition of the robot. Excursions of the distance assessment from a criteria indicate a failure or potential failure.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Arash Mahyari, Nevroz Sen, Thomas Locher, Wenzhi Gao, Dan Dai, Said Zahrai
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Publication number: 20130256766Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of a first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.Type: ApplicationFiled: May 20, 2013Publication date: October 3, 2013Applicant: International Business Machines CorporationInventors: Atul C. AJMERA, Christopher V. BAIOCCO, Xiangdong CHEN, Wenzhi GAO, Young W. TEH
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Patent number: 8461009Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.Type: GrantFiled: February 28, 2006Date of Patent: June 11, 2013Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Atul C. Ajmera, Christopher V. Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh
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Patent number: 7867835Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.Type: GrantFiled: February 29, 2008Date of Patent: January 11, 2011Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
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Patent number: 7795680Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: GrantFiled: December 7, 2007Date of Patent: September 14, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Publication number: 20100009527Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yong Meng Lee, Chung Woh Lai, Huang Liu, Wenzhi Gao, Zhao Lun, Johnny Widodo, Shailendra Mishra, Liang-Choo Hsia
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Publication number: 20090218636Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
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Publication number: 20090146262Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Huang Liu, Alex K.H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Patent number: 7531401Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.Type: GrantFiled: February 8, 2007Date of Patent: May 12, 2009Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
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Publication number: 20080191284Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., SAMSUNG ELECTRONICS CO., LTD.Inventors: Christopher Vincent Baiocco, Xiangdong Chen, Wenzhi Gao, Young Gun Ko, Young Way Teh
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Publication number: 20070254420Abstract: Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicants: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD.Inventors: Atul Ajmera, Christopher Baiocco, Xiangdong Chen, Thomas Dyer, Sunfei Fang, Wenzhi Gao
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Publication number: 20070202654Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Christopher Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh