Abstract: A microspheric ionomer having a cross-linked structure, a preparation method therefor, applications thereof, and a preparation system thereof. The ionomer comprises structure units A represented by formula (1), structure units B represented by formula (2), and a cross-linking structure provided by a cross-linking agent, M being separately selected from H, a metal cation, and a straight chain, a saturated alkyl of branched or ring-shaped C1-C20, R being H or a methyl; and metal cations are introduced to part of structure units A in the ionomer. The ionomer shows an outstanding effect on nucleation of PET, serves as a nucleating agent for PET modification, so as to obtain a corresponding PET composition.

Abstract: A method of forming a diffusion barrier layer on a dielectric or semiconductor substrate by a wet process. The method includes the steps of treating the dielectric or semiconductor substrate with an aqueous pretreatment solution comprising one or more adsorption promoting ingredients capable of preparing the substrate for deposition of the diffusion barrier layer thereon; and contacting the treated dielectric or semiconductor substrate with a deposition solution comprising manganese compounds and an inorganic pH buffer (optionally, with one or more doping metals) to the diffusion barrier layer thereon, wherein the diffusion barrier layer comprises manganese oxide. Also included is a two-part kit for treating a dielectric or semiconductor substrate to form a diffusion barrier layer thereon.

Abstract: A method of forming a diffusion barrier layer on a dielectric or semiconductor substrate by a wet process. The method includes the steps of treating the dielectric or semiconductor substrate with an aqueous pretreatment solution comprising one or more adsorption promoting ingredients capable of preparing the substrate for deposition of the diffusion barrier layer thereon; and contacting the treated dielectric or semiconductor substrate with a deposition solution comprising manganese compounds and an inorganic pH buffer (optionally, with one or more doping metals) to the diffusion barrier layer thereon, wherein the diffusion barrier layer comprises manganese oxide. Also included is a two-part kit for treating a dielectric or semiconductor substrate to form a diffusion barrier layer thereon.

Abstract: A method of forming a diffusion barrier layer on a dielectric or semiconductor substrate by a wet process. The method includes the steps of treating the dielectric or semiconductor substrate with an aqueous pretreatment solution comprising one or more adsorption promoting ingredients capable of preparing the substrate for deposition of the diffusion barrier layer thereon; and contacting the treated dielectric or semiconductor substrate with a deposition solution comprising manganese compounds and an inorganic pH buffer (optionally, with one or more doping metals) to the diffusion barrier layer thereon, wherein the diffusion barrier layer comprises manganese oxide. Also included is a two-part kit for treating a dielectric or semiconductor substrate to form a diffusion barrier layer thereon.

Abstract: A nickel electrodeposition composition for via fill or barrier nickel interconnect fabrication comprising: (a) a source of nickel ions; (b) one or more polarizing additives; and (c) one or more depolarizing additives. The nickel electrodeposition composition may include various additives, including suitable acids, surfactants, buffers, and/or stress modifiers to produce bottom-up filling of vias and trenches.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.