Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

Abstract: The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.

Abstract: There are disclosed a method and device for performing Copy-on-Write in a processor. The processor comprises: processor cores, L1 caches each of which is logically divided into a first L1 cache and a second L1 cache, and L2 caches. The first L1 cache is used for saving new data value, and the second L1 cache for saving old data value. The method can comprise the steps of: in response to a store operation from said processor core, judging whether a corresponding cache line in said L2 cache has been modified; if it is determined a corresponding L2 cache line in said L2 cache has not been modified, copying old data value in the corresponding L2 cache line to said second L1 cache, and writing new data value to the corresponding L2 cache line; and if it is determined a corresponding L2 cache line in said L2 cache has been modified, writing new data value to the corresponding L2 cache line directly.

Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

Abstract: An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

Abstract: The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: The present invention relates to a method and apparatus of lock transactions processing in a single or multi-core processor. An embodiment of the present invention is a processor with one or more processing cores, an address arbitrator, where one or more processing cores are configured to submit a lock transaction request to the address arbitrator corresponding to a specific instruction in response to the execution of the specific instruction. The lock transaction request includes a lock variable address asserted on an address bus. The processor further includes a lock controller for performing lock transaction processing in response to the lock transaction request, and notifying processing result to the processing core from which the lock transaction request was sent. The processor further includes a switching device, coupled to the address arbitrator and the lock controller, for identifying the lock transaction request and notifying the lock transaction request to the lock controller.