Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: The present disclosure relates to a layout design method, an integrated circuit, an operation chip, and a computing device. The layout design method comprises generating a primary layout on the basis of a circuit diagram netlist by using a primary standard cell library, the circuit diagram netlist comprising a first standard cell and a second standard cell, and the primary standard cell library comprising a first standard layout of the first standard cell and a second standard layout of the second standard cell. The method further comprises consolidating the first standard layout and the second standard layout on the basis of a splicing relationship between the first standard layout and the second standard layout in the primary layout to optimize the consolidated layout.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Abstract: A multi-bit register (200), a chip, and a computing apparatus, the multi-bit register (100) including: a plurality of register units (210-1, 210-2, . . . , 210-N), each of which is configured to store a bit of data, and the plurality of register units (210-1, 210-2, . . . , 210-N) being connected in parallel to each other; a clock buffer configured to provide a clock signal for the plurality of register units (210-1, 210-2, . . . , 210-N), wherein the plurality of register units (210-1, 210-2, . . . , 210-N) is arranged into an array of register units, and the clock buffer is arranged at an intervening position of the array of register units (210-1, 210-2, . . . , 210-N).

Abstract: A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.

Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Abstract: Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

Abstract: Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

Abstract: Techniques pertaining to a voltage regulator with a current limiting circuit having low quiescent current are disclosed.

Abstract: A battery protection circuit with quickly testable design is disclosed. According to one embodiment, the battery protection circuit includes a battery voltage detection circuit configured to detect a battery voltage, output an effective trigger signal if the battery voltage reaches a voltage protection threshold, and output an ineffective trigger signal otherwise; a delay circuit configured to receive the trigger signal, output an effective status signal if the trigger signal is maintained effective continuously over a period of time, and outputs an ineffective status signal otherwise; a protection driver configured to receive the trigger signal and the status signal, enter a driving state when both the trigger signal and the status signal are effective, enter a non-driving state when both the trigger signal and the status signal are ineffective, and enter a ready driving state when the trigger signal is effective and the status signal is ineffective.

Abstract: Techniques pertaining to driving LEDs on multiple branches of a circuit are disclosed. According to one aspect of the present invention, an LED drive circuit includes a boost circuit configured for receiving an input voltage and providing an output voltage according to a control signal, a selector configured for alternatively selecting one of the feedback signals as an output feedback signal and switching on a corresponding branch circuit, and a pulse-width modulation (PWM) controller configured for generating a pulse-width modulation signal as the control signal for the boost circuit according to the output feedback signal of the selector, essentially to match respective currents in the multiple branches.

Abstract: A scan mode is used in a voltage detection circuit. An oscillator in the circuit is always on and a system including the voltage detection circuit detects various abnormal conditions, such as overcharging, overdischarging and overcurrent one by one for some clocks. To reduce the power consumption, the voltage detection circuit is turned on only once for several clocks. The on-time is very short and lasts about only one tenth of a clock cycle time. In other times, the voltage detection circuit is turned off to save power consumption.

Abstract: Techniques pertaining to a voltage regulator with a current limiting circuit having low quiescent current are disclosed.

Abstract: Techniques pertaining to driving LEDs on multiple branches of a circuit are disclosed. According to one aspect of the present invention, an LED drive circuit includes a boost circuit configured for receiving an input voltage and providing an output voltage according to a control signal, a selector configured for alternatively selecting one of the feedback signals as an output feedback signal and switching on a corresponding branch circuit, and a pulse-width modulation (PWM) controller configured for generating a pulse-width modulation signal as the control signal for the boost circuit according to the output feedback signal of the selector, essentially to match respective currents in the multiple branches.

Abstract: Improved designs of an LDO voltage regulator with ultra low quiescent current are disclosed. According to one embodiment, an LDO voltage regulator is designed to completely cancel an intermediate gain stage while decreasing a quiescent current and to stabilize a loop circuit by means of two zeros introduced in a frequency transfer function thereof. Such a LDO voltage regulator does not increase the power consumption and applicable in many circuits used in electronic devices.

Abstract: Techniques pertaining designs of LDO voltage regulators are described.