Abstract: In some embodiments, an apparatus for performing convolution operations is provided. The apparatus may include multiple crossbar arrays and select circuits. The select circuits are configured to select a first plurality of cross-point devices and a second plurality of cross-point devices in response to receiving a control signal indicating that a regular convolution is to be performed, and to select the first plurality of cross-point devices and a third plurality of cross-point devices in response to receiving a control signal indicating that a depthwise convolution is to be performed. The first plurality of cross-point devices is connected to a first plurality of word lines and a first bit line. The second plurality of cross-point devices is connected to the first plurality of word lines and a second bit line. The third plurality of cross-point devices is connected to a second plurality of word lines and the second bit line.

Abstract: According to some aspects of the disclosure, a crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of switches connected to the plurality of word lines. Each of the plurality of cross-point devices is connected to at least one of the word lines and at least one of bit lines and may include a resistive random-access memory (RRAM) device. Each of the switches is selectively connected to ground or a reference voltage. A digital input may be provided to a cross-point device of the crossbar circuit by selectively connecting a word line connected to the cross-point device to ground or the reference voltage.

Abstract: The present disclosure provides for transimpedance amplifiers for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit line. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a supply voltage.

Abstract: The present disclosure relates to voltage-mode crossbar circuits that may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of sensing circuits configured to amplify bit line voltages settled on the bit lines in response to an application of input voltages to the cross-point devices via the word lines and generate digital outputs representative of the amplified bit line voltages. Each cross-point device is connected to one of the word lines and one of the bit lines and may include a resistive random-access memory (RRAM) device. Each cross-point device may further be connected to a local select line that may enable a group of cross-point devices connected to one or more bit lines. A cross-point device may be enabled when both a global select line and the local select line connected to the cross-point device are enabled.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus for performing convolution operations is provided. The apparatus includes a first crossbar circuit comprising a first plurality of cross-point devices; a second crossbar circuit comprising a second plurality of cross-point devices; and a word line logic to apply input signals to the first crossbar circuit and the second crossbar circuit. The word line logic is configured to provide input signals representative of input data to be convolved using one or more two-dimensional convolution kernels and one or more depth-wise convolution kernels. The first crossbar circuit is configured to output a first plurality of output signals representative of a convolution of the input data and the two-dimensional convolution kernels. The second crossbar circuit is configured to output a second plurality of output signals representative of a convolution of the input data and the depth-wise convolution kernels.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus for performing convolution operations is provided. The apparatus includes a first crossbar circuit comprising a first plurality of cross-point devices; a second crossbar circuit comprising a second plurality of cross-point devices; and a word line logic to apply input signals to the first crossbar circuit and the second crossbar circuit. The word line logic is configured to provide input signals representative of input data to be convolved using one or more two-dimensional convolution kernels and one or more depth-wise convolution kernels. The first crossbar circuit is configured to output a first plurality of output signals representative of a convolution of the input data and the two-dimensional convolution kernels. The second crossbar circuit is configured to output a second plurality of output signals representative of a convolution of the input data and the depth-wise convolution kernels.

Abstract: The present disclosure provides a comparator including a non-volatile memory device. The comparator is configured to compare an analog input voltage and a reference voltage and produce a digital output indicative of the comparison result. The digital output may represent a resistance state of the non-volatile memory device in response to the application of the reference voltage and the analog input voltage to the comparator. The present disclosure further provides analog-to-digital converters (ADCs) utilizing the comparator. The non-volatile memory device includes, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc.

Abstract: The present disclosure provides a voltage divider circuit utilizing non-volatile memory devices. The non-volatile memory device may include, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc. The voltage divider circuit may include one or more first non-volatile memory devices that form a resistor ladder. The resistor ladder may produce a plurality of reference voltages when the resistor ladder is connected between two voltages.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus for performing convolution operations is provided. The apparatus includes a first crossbar circuit comprising a first plurality of cross-point devices; a second crossbar circuit comprising a second plurality of cross-point devices; and a word line logic to apply input signals to the first crossbar circuit and the second crossbar circuit. The word line logic is configured to provide input signals representative of input data to be convolved using one or more two-dimensional convolution kernels and one or more depth-wise convolution kernels. The first crossbar circuit is configured to output a first plurality of output signals representative of a convolution of the input data and the two-dimensional convolution kernels. The second crossbar circuit is configured to output a second plurality of output signals representative of a convolution of the input data and the depth-wise convolution kernels.

Abstract: Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

Abstract: In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

Abstract: Technologies relating to AI fusion pixel sensor for MLP using active pixel sensors with memristors are disclosed. An example apparatus includes: many of active pixel sensors, wherein each active pixel sensors includes: a photodiode configured to receive image signal; a transfer gate; a selector controller; a reset controller; a voltage readout end; a first 1T1R cell, a second 1T1R cell, and a third 1T1R cell connected to the voltage readout end; and a first current readout end, a second current readout end, and a third current readout end connected to the first 1T1R cell, the second 1T1R cell, and the third 1T1R cell respectively; a first total current readout end, a second total current readout end, and a third total current readout end, whose total current equals the sum of the currents of all current readout ends in each active pixel sensors.

Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.

Abstract: Technologies relating to crossbar array circuits with nTnR design to reduce sneak current path and minimize area size are disclosed. An example crossbar array circuit includes: a first transistor comprising a first source terminal, a first drain terminal and a first gate terminal; a first RRAM device connected to the first source terminal of the first transistor; a second transistor comprising a second source terminal, a second drain terminal and a second gate terminal; a second RRAM device connected to the second source terminal of the second transistor; a word line connected to the first drain terminal of the first transistor and the second drain terminal of the second transistor; a first bit line connected to the first RRAM device; and a second bit line connected to the second RRAM device, wherein the first gate terminal of the first transistor is configured to be connected to a first selective voltage source, and the second gate terminal is configured to be connected to a second selective voltage source.

Abstract: Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.