Abstract: A directional shockproof tilting display tag, comprising a container provided with a detector therein; the detector comprises a first placement chamber, a second placement chamber, and a baffle; the first placement chamber comprises a first side plate and a first mass block; the first side plate is externally provided with a first extension portion; the second placement chamber comprises a second side plate and a second mass block; the second side plate is externally provided with a second extension portion; the placement chambers are also provided with bar codes; part of the patterns of the bar codes are covered by the mass blocks; a rotary shaft is disposed directly above the placement chambers; the container is also provided with a shockproof structure therein. The display tag has a simple structure and strong shockproof capability. The arrangement of the bar codes ensures the detector can quickly detect an object tilting.

Abstract: A directional shockproof tilting display tag, comprising a container provided with a detector therein; the detector comprises a first placement chamber, a second placement chamber, and a baffle; the first placement chamber comprises a first side plate and a first mass block; the first side plate is externally provided with a first extension portion; the second placement chamber comprises a second side plate and a second mass block; the second side plate is externally provided with a second extension portion; the placement chambers are also provided with bar codes; part of the patterns of the bar codes are covered by the mass blocks; a rotary shaft is disposed directly above the placement chambers; the container is also provided with a shockproof structure therein. The display tag has a simple structure and strong shockproof capability. The arrangement of the bar codes ensures the detector can quickly detect an object tilting.

Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Abstract: A hardware and software co-test method for FPGA comprises the following steps of: setting up a HW/SW co-test system comprising a PC, a software part, HW/SW communication modules, a hardware accelerator for testing a DUT FPGA which is mapped with a configuration file of DUT; predefining a table of test vectors for FPGA by software part in PC; generating configuration files based on the tables of test vector for I/O module, CLB and routing matrix, and then sending the configuration file into DUT FPGA to configure the FPGA; testing DUT FPGA in terms of the tables of test vector for lo I/O module, CLB and routing matrix, and returning results to the software part; and comparing the test results with expected data in the software part, generating a test report, and during the above steps, the error cells in the FPGA are capable of being automatically positioned.