Patents by Inventor Wenchi Ting
Wenchi Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030096473Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.Type: ApplicationFiled: November 16, 2001Publication date: May 22, 2003Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Wong-Cheng Shih, Wenchi Ting, Tzyh-Cheang Lee, Chin-Hsien Lin, Shyh-Chyi Wong
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Publication number: 20030077882Abstract: A method of fabricating a strained-silicon structure comprising the following steps. A substrate having an insulator layer formed thereover is provided. A silicon-on-insulator layer is formed over the insulator layer. A first SiGe layer is formed over the silicon-on-insulator layer. The first SiGe layer being strained. At least the first SiGe layer is annealed to convert the strained SiGe layer to a relaxed first SiGe layer. A second SiGe layer, having the same composition as the first SiGe layer, is formed over the first SiGe layer. The second SiGe layer being relaxed. An epitaxial silicon layer is grown over the second SiGe layer. The epitaxial silicon layer being strained to complete formation of the strained-silicon structure.Type: ApplicationFiled: July 26, 2001Publication date: April 24, 2003Applicant: Taiwan Semiconductor Manfacturing CompanyInventors: Wong-Cheng Shih, Wenchi Ting
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Patent number: 6436787Abstract: A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening.Type: GrantFiled: July 26, 2001Date of Patent: August 20, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wong-Cheng Shih, Tzyh-Cheang Lee, Wenchi Ting, Chih-Hsien Lin, Shyh-Chyi Wong
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Publication number: 20010023107Abstract: Alternative methods are provided for fabricating a hybrid isolation structure on a semiconductor substrate, wherein, the hybrid isolation structure includes a shallow trench isolation (STI) and a field oxide isolation formed by local oxidation of silicon (LOCOS). In detail, the STI is formed within a device region that is operated at a low working voltage, a logic device region, to efficiently enhance the device density. On the other hand, the LOCOS isolation is formed within a device region that is operated at a high working voltage, a memory device region, to ensure the reliability and performance of the devices.Type: ApplicationFiled: April 26, 1999Publication date: September 20, 2001Inventors: GARY HONG, WENCHI TING
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Patent number: 6232183Abstract: A method for fabricating a flash memory is disclosed, in which a stacked gate structure comprising a floating gate and a control gate on the substrate is first formed. Ions are implanted into the substrate at one side of the stacked gate. A drain having a heavily doped region and a lightly doped region are subsequently formed. Spacers one each side of the stacked gate structure are formed. By using a photoresist layer covering the spacer at the drain end, the spacer at the source end can be reduced by an etching process. The source region of the flash memory is formed by implanting ions into the substrate using the reduced spacer as a mask.Type: GrantFiled: January 8, 1999Date of Patent: May 15, 2001Assignee: United Microelectronics Crop.Inventors: Hwi-Huang Chen, Wenchi Ting
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Patent number: 6091636Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.Type: GrantFiled: March 26, 1998Date of Patent: July 18, 2000Inventors: David K. Y. Liu, Wenchi Ting
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Patent number: 6046938Abstract: A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode selector transistor isolates the common drain and the memory unit. Two terminals the depletion mode selector transistor are coupled to the common drain and the memory unit, respectively.Type: GrantFiled: November 13, 1998Date of Patent: April 4, 2000Assignee: United Semiconductor Corp.Inventors: Gary Hong, Wenchi Ting, Joe Ko
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Patent number: 6008522Abstract: The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a surface. Afterwards, a second conductive layer is formed on the surface and fills the trench, wherein the second conductive layer makes contact with the top corner, and a shallow junction region is located at the top corner and makes contact with the second conductive layer.Type: GrantFiled: July 10, 1998Date of Patent: December 28, 1999Assignee: United Semiconductor Corp.Inventors: Gary Hong, Yau-Kae Sheu, Wenchi Ting
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Patent number: 5882972Abstract: A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer.Type: GrantFiled: July 10, 1998Date of Patent: March 16, 1999Assignee: United Semiconductor Corp.Inventors: Gary Hong, Yau-Kae Sheu, Wenchi Ting
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Patent number: 5852313Abstract: A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.Type: GrantFiled: November 12, 1997Date of Patent: December 22, 1998Assignee: United Semiconductor Corp.Inventors: Gary Hong, Patrick Wang, Wenchi Ting
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Patent number: 5844271Abstract: An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used.Type: GrantFiled: August 21, 1995Date of Patent: December 1, 1998Assignee: Cypress Semiconductor Corp.Inventors: Rakesh Sethi, Wenchi Ting
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Patent number: 5814854Abstract: The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.Type: GrantFiled: September 9, 1996Date of Patent: September 29, 1998Inventors: David K. Y. Liu, Wenchi Ting
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Patent number: 5751631Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.Type: GrantFiled: October 21, 1996Date of Patent: May 12, 1998Inventors: David K. Y. Liu, Wenchi Ting