Abstract: A method for forming a silicide bridge bewteen a diffusion region and an adjacent poly-filled trench separated by a thin dielectric. Silicon is selectively grown over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth over other insulator regions. A refractory metal layer is then deposited and sintered under conditions that limit lateral silicide growth, forming the bridge. This process avoids the random fails produced by previous processes while enhancing the compatibility of bridge formation with shallow junctions, without introducing extra masking steps or other process complexities.

Abstract: A simple process is provided for making two self-aligned recessed oxide isolation regions of different thicknesses which includes the steps of defining first and second spaced apart regions on the surface of a semiconductor substrate, forming a protective layer over the first region, forming a first insulating layer of a given thickness within the second region while the first region is protected by the protective layer, removing the protective layer from the first region and forming a second insulating layer thinner than that of the first layer within the first region. Field regions may be ion implanted prior to forming the insulating layers.

Abstract: A process is provided for making a conductive structure for a semiconductor circuit, such as a one device dynamic random access memory cell, which includes the steps of depositing a conductive layer on a surface of a semiconductor substrate having a given type conductivity spaced from a storage node, depositing a layer of polysilicon over the conductive layer, depositing a layer of photoresist over the polysilicon layer, defining an opening in the photoresist layer and implanting ions of a conductivity type opposite to that of the given type conductivity through the opening and the polysilicon layer into the semiconductor substrate to form therein a conductive pocket or region having the opposite type conductivity resulting in, e.g., a highly conductive bit/sense line of a memory cell.

Abstract: An electrically alterable double dense memory is provided which includes a field effect transistor having first and second spaced apart diffusion regions of a first conductivity defining a channel region at the surface of a semiconductor substrate having a second conductivity. First and second floating gates are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region. First and second dual charge injector structures or enhanced conduction insulators are disposed between the first and second floating gates and a common control gate of the transistor. A word line is connected to the control gate and first and second bit lines are connected to the first and second diffusion regions. By applying appropriate pulses to the word and bit lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region associated with the selected floating gate and then discharged at will.

Abstract: A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits. The method provides for the application of a masking or photoresist layer over the surface of a substrate containing portions of a conductor to be removed such that the masking layer completely covers the conductor. Next a uniform thickness of the masking layer is removed to expose only the raised portions of the conductor which are subsequently selectively etched through the remainder of the masking layer. Application of the method to a manufacturing process for a dynamic MOSFET memory array is also described in which bit sense line capacitance is substantially reduced.