Abstract: Many integrated circuits, particularly digital memories, include millions of field-effect transistors which operate simultaneously and thus consume considerable power. One way to reduce power consumption is to lower transistor threshold, or turn-on, voltage, and then use lower-voltage power supplies. Although conventional techniques of lowering threshold voltage have enabled use of 2-volt power supplies, even lower voltages are needed. Several proposals involving a dynamic threshold concept have been promising, but have failed, primarily because of circuit-space considerations, to yield practical devices. Accordingly, the present invention provides a space-saving structure for a field-effect transistor having a dynamic threshold voltage. One embodiment includes a vertical gate-to-body coupling capacitor that reduces the surface area required to realize the dynamic threshold concept. Other embodiments include an inverter, voltage sense amplifier, and a memory.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred—implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar.

Abstract: Applications and methods for DRAM technology compatible non-volatile memory cells are presented. An example illustrating the applications and methods includes a circuit switch. The circuit switch has a non-volatile memory cell which a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

Abstract: A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.

Abstract: Many integrated circuits include a type of transistor known as a metal-oxide-semiconductor, field-effect transistor, or “mosfet,” which has an insulated gate member that controls its operation. Early mosfets had aluminum gates. But because the aluminum made the mosfets unreliable and difficult to manufacture, aluminum was abandoned in favor of polysilicon. Unfortunately, polysilicon has ten-times more electrical resistance than aluminum, which not only wastes power but also slows operation of the integrated circuits. Several efforts have been made to use materials less-resistive than polysilicon, but these have failed to yield a practical solution, since some of the materials have high electrical resistance and prevent low-voltage operation.

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

Abstract: A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar.

Abstract: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Abstract: A memory cell. The memory cell has a flip-flop that includes a cross-coupled pair of inverters. The inverters each include a pair of complementary, vertical transistors. A gate contact interconnects the gates of the inverters and acts as the input of the inverter. A shunt interconnects a first source/drain region of the complementary transistors and acts as the output of the inverter. A first vertical, access transistor is also included. The first vertical, access transistor has a gate that is coupled to a word line, a first source/drain region that is coupled to the output of one of the inverters, and a second source/drain region that is coupled to a first bit line. A second vertical, access transistor is also provided. The second vertical, access transistor has a gate that is coupled to the word line, a first source/drain region that is coupled to the output of the other inverter, and a second source/drain region that is coupled to a second bit line.

Abstract: A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.

Abstract: A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.