Patents by Inventor Wendell Phillips Noble

Wendell Phillips Noble has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench EPROM
    Patent number: 5932908
    Abstract: A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: August 3, 1999
    Assignee: International Business Machines Corporation
    Inventor: Wendell Phillips Noble
  • Method of making trench EPROM simultaneously with forming a DRAM cell
    Patent number: 5930619
    Abstract: A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.
    Type: Grant
    Filed: February 8, 1996
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventor: Wendell Phillips Noble
  • Method for making MOSFET device having controlled parasitic isolation threshold voltage
    Patent number: 5726095
    Abstract: A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: March 10, 1998
    Assignee: International Business Machines Corporation
    Inventor: Wendell Phillips Noble
  • MOSFET device having controlled parasitic isolation threshold voltage
    Patent number: 5650654
    Abstract: A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: July 22, 1997
    Assignee: International Business Machines Corporation
    Inventor: Wendell Phillips Noble