Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Abstract: A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.

Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal.

Abstract: A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.