Patents by Inventor Wendy Elsasser
Wendy Elsasser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250047469Abstract: Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.Type: ApplicationFiled: May 21, 2024Publication date: February 6, 2025Inventors: Evan Lawrence Erickson, Michael Alexander Hamburg, Taeksang Song, Wendy Elsasser
-
Publication number: 20240394195Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.Type: ApplicationFiled: May 15, 2024Publication date: November 28, 2024Inventors: Steven C. WOO, Michael Raymond MILLER, Taeksang SONG, Wendy ELSASSER, Maryam BABAIE
-
Publication number: 20240311301Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. In response to some write and/or read access commands, the DRAM device is configured to copy a cache line (e.g., dirty cache line) from the main DRAM memory array, place it in a flush buffer, and replace the copied cache line in the main DRAM memory array with a new (e.g., different) cache line of data. In response to conditions and/or events (e.g., explicit command, refresh, write-to-read command sequence, unused data bus bandwidth, full flush buffer, etc.) the DRAM device transmits the cache line from the flush buffer to the controller. The controller may then transmit the cache line to other cache levels.Type: ApplicationFiled: March 7, 2024Publication date: September 19, 2024Inventors: Michael Raymond MILLER, Steven C. Woo, Wendy Elsasser, Taeksang Song
-
Publication number: 20240160388Abstract: A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.Type: ApplicationFiled: October 30, 2023Publication date: May 16, 2024Inventors: Taeksang Song, Evan Lawrence Erickson, Wendy Elsasser
-
Patent number: 10795815Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.Type: GrantFiled: May 27, 2016Date of Patent: October 6, 2020Assignee: ARM LimitedInventors: Jonathan Curtis Beard, Wendy Elsasser, Stephan Diestelhorst
-
Patent number: 10552152Abstract: A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.Type: GrantFiled: May 27, 2016Date of Patent: February 4, 2020Assignee: Arm LimitedInventors: Jonathan Curtis Beard, Wendy Elsasser, Eric Van Hensbergen, Stephan Diestelhorst
-
Patent number: 10445094Abstract: A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.Type: GrantFiled: May 27, 2016Date of Patent: October 15, 2019Assignee: Arm LimitedInventors: Jonathan Curtis Beard, Wendy Elsasser, Shibo Wang
-
Publication number: 20170344366Abstract: A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Applicant: ARM LimitedInventors: Jonathan Curtis BEARD, Wendy ELSASSER, Eric VAN HENSBERGEN, Stephan DIESTELHORST
-
Publication number: 20170344367Abstract: A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Applicant: ARM LimitedInventors: Jonathan Curtis BEARD, Wendy ELSASSER, Shibo WANG
-
Publication number: 20170344480Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Applicant: ARM LimitedInventors: Jonathan Curtis BEARD, Wendy ELSASSER, Stephan DIESTELHORST
-
Patent number: 9280454Abstract: A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory array of the associated memory chip. The method and system further includes providing the determined bit ordering to the SoC.Type: GrantFiled: March 2, 2012Date of Patent: March 8, 2016Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Wendy Elsasser, Marc Greenberg