Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

Abstract: Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.

Abstract: Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.

Abstract: Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.

Abstract: Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.

Abstract: A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

Abstract: A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

Abstract: Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.

Abstract: Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.