Abstract: A cell structure and a semiconductor device using the same. The cell structure comprises a semiconductor substrate; a plurality of slot units are provided at the top end of the semiconductor substrate; a corresponding carrier barrier region is provided at the bottom of each slot unit; a conductive material is provided in each slot; source body regions are provided between the adjacent slot units; one or more source regions are closely attached on the surface of each source body region, and the source regions and the source body regions are in contact with a first metal layer at the top of the semiconductor substrate; a first semiconductor region and a second metal layer in contact with the first semiconductor region are provided at the bottom of the semiconductor substrate.

Abstract: A cell structure and related semiconductor device. The cell structure includes a semiconductor substrate, which includes a plurality of first and second trench units. A carrier barrier region and an electric field shielding region corresponding to the first and second trench units are provided at a bottom of each trench. Conductive materials are provided in the trenches to correspondingly form two gate regions. A source-body region is provided between adjacent first trench units and in contact with a first metal layer on a top portion of the semiconductor substrate. A floating region is provided between the first and second trench units and is isolated from a second metal layer by an insulating dielectric. More than one source region is provided in the surface of the source-body region close to a side edge of at least one of the first trench units and the second trench units.

Abstract: A current protection-type semiconductor device includes an internal resistance that may be instantaneously changed from a low resistance to a high resistance when an overload current appears in a circuit, thereby blocking other elements in a surge current protection circuit. The device comprises an (N+)-type semiconductor substrate, and an N-type voltage-sustaining layer arranged above the (N+)-type semiconductor substrate which serves as a main layer of the device for sustaining a voltage. At least one N-type converter area and at least one P-type source body area are arranged on an upper surface of the N-type voltage-sustaining layer. At least one P-type buried layer is further arranged in the N-type voltage-sustaining layer, and the P-type buried layer is surrounded by the N-type voltage-sustaining layer. Under different voltages between two ports of a TBC, the internal resistance of the TBC is switched between two different states of low resistance and high resistance.

Abstract: A semiconductor device and a junction edge region thereof. The junction edge region comprises a semiconductor substrate and an epitaxial layer above said substrate, the semiconductor substrate and the epitaxial layer being in a laminated structure and of the same conductor type; several floating regions spaced apart are provided between the semiconductor substrate and the epitaxial layer, a transition region is provided on the surface of the epitaxial layer adjacent to an active region portion, and the semiconductor substrate is additionally provided with a first semiconductor region.

Abstract: This application provides a cell structure and its related semiconductor device. Said cell structure includes a semiconductor substrate. In said semiconductor substrate, there are a plurality of first and second trench units. A carrier barrier region and an electric field shielding region corresponding to the first and second trench units are provided at a bottom of each trench. Conductive materials are provided in the trenches to correspondingly form two gate regions. A source-body region is provided between adjacent first trench units and in contact with a first metal layer on a top portion of the semiconductor substrate. A floating region is provided between the first and second trench units and is isolated from a second metal layer by an insulating dielectric. More than one source region is provided in the surface of the source-body region close to a side edge of at least one of the first trench units and the second trench units.

Abstract: A semiconductor device and a junction edge region thereof. The junction edge region comprises a semiconductor substrate and an epitaxial layer above said substrate, the semiconductor substrate and the epitaxial layer being in a laminated structure and of the same conductor type; several floating regions spaced apart are provided between the semiconductor substrate and the epitaxial layer, a transition region is provided on the surface of the epitaxial layer adjacent to an active region portion, and the semiconductor substrate is additionally provided with a first semiconductor region.

Abstract: A cell structure and a semiconductor device using the same. The cell structure comprises a semiconductor substrate; a plurality of slot units are provided at the top end of the semiconductor substrate; a corresponding carrier barrier region is provided at the bottom of each slot unit; a conductive material is provided in each slot; source body regions are provided between the adjacent slot units; one or more source regions are closely attached on the surface of each source body region, and the source regions and the source body regions are in contact with a first metal layer at the top of the semiconductor substrate; a first semiconductor region and a second metal layer in contact with the first semiconductor region are provided at the bottom of the semiconductor substrate.

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.