Patents by Inventor Wenfen CHANG

Wenfen CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
    Patent number: 9570429
    Abstract: The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 14, 2017
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianhong Mao, Fengqin Han, Zhiwei Wang, Wenfen Chang
  • Methods of Fabrication and Testing of Three-Dimensional Stacked Integrated Circuit System-In-Package
    Publication number: 20150311188
    Abstract: The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 29, 2015
    Inventors: Jianhong MAO, Fengqin HAN, Zhiwei WANG, Wenfen CHANG