Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Abstract: The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.

Abstract: A memory device and a fabrication method thereof, wherein the memory device includes a gate oxide layer disposed on a surface of the substrate and a gate disposed on a portion of the gate oxide layer. A buried drain line is located in the substrate beside both sides of the gate and a spacer is disposed beside the sidewalls of the gate. A deep doped region is located in the substrate below a portion of the buried drain line, wherein the buried drain line and the deep doped region together serve as a word line for the memory device. An insulation layer is disposed above the bit line and a word line is disposed above the gate and the insulation layer, perpendicular to a direction of the bit line.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Abstract: A method for reducing defects and particles during fabrication of a semiconductor device with an ONO film is disclosed. A substrate divided into a first region and a second region is provided. The first region has a plurality of floating gates and the second region has an oxide layer, a first polysilicon layer, and a second polysilicon layer. An oxide-nitride-oxide (ONO) film is formed over the floating gates and the second polysilicon layer. A patterned photoresist layer masking the first region is formed and a dry etch process is performed to remove the ONO layer, the first polysilicon layer, and the second polysilicon layer within the exposed second region. A series of cleaning steps are performed in a cascade manner.

Abstract: A shallow trench isolation (STI) method for use in semiconductor processes, with the method including the following steps. Having a substrate with a top surface, and forming a trench-patterned mask layer on the top surface to expose an unmasked trench region of the substrate, the mask layer including a pad oxide layer and a silicon nitride layer formed on the pad oxide layer. Etching the unmasked region of the substrate to form a trench on the substrate, depositing an HTO (high temperature oxide) film over the substrate to cover the trench and the mask layer, depositing a dielectric layer to fill the trench and to cover the HTO film, planarizing the dielectric layer to expose the silicon nitride layer, and stripping the silicon nitride.

Abstract: An improved STI method having an ISSG film as an interface reinforcement layer is disclosed. The present invention includes the following steps of forming a trench-patterned mask layer on the top surface of a substrate exposing an unmasked trench region of the substrate. The mask layer is a pad oxide layer and a silicon nitride layer formed on the pad oxide layer. The unmasked region of the substrate is etched to form a trench on the substrate and the silicon nitride layer and the substrate of the trench are simultaneously oxidized to form an ISSG in-situ steam growth (ISSG) film. A dielectric layer is deposited that fills the trench and covers the mask layer. The dielectric layer is planarized to expose the silicon nitride layer, then the silicon nitride is stripped.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an ISSG film is disclosed. The random bit failures are caused by HF acid penetration. The ISSG film, which functions as a interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the ISSG film, the flash memory is free of acid-corroded seams.

Abstract: A simplified flash memory fabrication process is disclosed. The method includes the following steps: 1) forming a stacked layer on a substrate in the channel region, and the stacked layer is a polysilicon layer and a sacrificial layer formed atop the polysilicon layer; 2) depositing a dielectric layer to cover the channel region and the bit line region; 3) performing an isotropic dry etching process to etch away a predetermined thickness of the dielectric layer to expose a portion of the sacrificial layer, and at the same time, dividing the dielectric layer into a first portion dielectric layer positioned atop the sacrificial layer and a second portion dielectric layer that is not connected with the first portion dielectric layer; and 4) completely removing the sacrificial layer and the first portion dielectric layer.

Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Abstract: A semiconductor wafer includes a substrate, a polysilicon layer, and a sacrificial layer on the polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. A passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the sacrificial layer. The passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer, followed by removing the passivation layer and removing the sacrificial layer. A recess is thus formed with the polysilicon layer as the bottom of the recess and the remaining dielectric layer as the walls. Finally, another polysilicon layer is formed on the semiconductor wafer to form a floating gate.

Abstract: The present invention provides afirst dielectric layer, a stop layer and a second dielectric layer arethen formed on the conductive layer disposed on a semiconductor substrate, respectively. By performing a first lithography/etching process to etch portions of the second dielectric layer in a predetermined area, a wire trench is formed in the predetermined area in the second dielectric layer. A first barrier layer is then formed to cover both a surface of the wire trenchand a surface of the second dielectric layer. By performing a second lithography/etching process to etch through the first barrier layer and the first dielectric layer down to the conductive layer, a via is formed at a bottom of the wire trench. A second barrier layer is formed thereafter to cover both a wall and a bottom of the via, and to cover the first barrier layer. Finally, an etching back process is performed to etch the second barrier layer down to the surface of the conductive layer.

Abstract: A semiconductor wafer is provided, the semiconductor wafer including a substrate, a first polysilicon layer having an approximately rectangular cross-section positioned on the substrate, and a sacrificial layer positioned on the first polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. Following this, a passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the upper portion of the sacrificial layer. Then, both the passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer followed by removing the passivation layer from the surface of the semiconductor wafer and removing the sacrificial layer from the first polysilicon layer.