Patents by Inventor Weng Khoon Mong

Weng Khoon Mong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817360
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 14, 2023
    Assignee: Nexperia B.V.
    Inventors: Loh Choong Keat, Edward Then, Weng Khoon Mong
  • Patent number: 10798814
    Abstract: A method of manufacturing a System in Package (SiP) module includes: welding required electronic units by the SiP module onto a top surface of a Printed Circuit Board (PCB), with welding spots being reserved on a bottom surface of the PCB for obtaining a PCB assembly (PCBA) of the SiP module; pasting tightly a functional film on a surface of the electronic units of the PCBA; filling on plastic materials on the top surface of the PCBA, ensuring that the plastic materials covers the electronic units and the functional film on the top surface of the PCBA, and obtaining solidified PCBA after the plastic materials are solidified; and cutting the solidified PCBA for obtaining a plurality of the SiP modules.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 6, 2020
    Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Jing Cao, Weng-Khoon Mong, Dong-Feng Ling
  • Publication number: 20190387610
    Abstract: A method of manufacturing a System in Package (SiP) module includes: welding required electronic units by the SiP module onto a top surface of a Printed Circuit Board (PCB), with welding spots being reserved on a bottom surface of the PCB for obtaining a PCB assembly (PCBA) of the SiP module; pasting tightly a functional film on a surface of the electronic units of the PCBA; filling on plastic materials on the top surface of the PCBA, ensuring that the plastic materials covers the electronic units and the functional film on the top surface of the PCBA, and obtaining solidified PCBA after the plastic materials are solidified; and cutting the solidified PCBA for obtaining a plurality of the SiP modules.
    Type: Application
    Filed: December 3, 2018
    Publication date: December 19, 2019
    Inventors: JING CAO, WENG-KHOON MONG, DONG-FENG LING
  • Publication number: 20190189530
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Applicant: NEXPERIA B.V.
    Inventors: Loh Choong KEAT, Edward THEN, Weng Khoon MONG
  • Patent number: 9397016
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee Ong
  • Publication number: 20150076692
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 19, 2015
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee Ong
  • Patent number: 8847368
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee One
  • Publication number: 20120319276
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 20, 2012
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee One
  • Patent number: 8258019
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee Ong
  • Publication number: 20090321928
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee Ong
  • Patent number: 7172951
    Abstract: An apparatus and a system for separating dice from a substrate are described herein.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventors: Oi Fong Chin, Yew Wee Cheong, Weng Khoon Mong
  • Patent number: 7005317
    Abstract: Methods and apparatus for separating dice from a substrate are described herein.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Oi Fong Chin, Yew Wee Cheong, Weng Khoon Mong
  • Patent number: 6713366
    Abstract: A method that includes, obtaining a substrate, placing a reinforcing layer over a first side of the substrate; and thinning the substrate by removing material from an opposite side of the substrate.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: March 30, 2004
    Assignee: Intel Corporation
    Inventors: Weng Khoon Mong, Yew Wee Cheong, Eng Chiang Gan, Mun Leong Loke
  • Publication number: 20030235937
    Abstract: A method that includes, obtaining a substrate, placing a reinforcing layer over a first side of the substrate; and thinning the substrate by removing material from an opposite side of the substrate.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 25, 2003
    Inventors: Weng Khoon Mong, Yew Wee Cheong, Eng Chiang Gan, Mun Leong Loke