Patents by Inventor Weng-Liang Fang

Weng-Liang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7141495
    Abstract: Methods of forming a contact structure, contact structures and apparatuses applied thereto are disclosed. The method of forming a contact structure forms a dielectric layer on a substrate. A metal contact with metal oxide thereon is formed in the dielectric layer. The solubility of the metal oxide is enhanced by using H2O with a temperature higher than about 10° C. or a chemical with a temperature higher than about 15° C.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shuang-Neng Peng, Chun-Hung Chen, Soon Kang Huang, Weng-Liang Fang
  • Publication number: 20060046492
    Abstract: Methods of forming a contact structure, contact structures and apparatuses applied thereto are disclosed. The method of forming a contact structure forms a dielectric layer on a substrate. A metal contact with metal oxide thereon is formed in the dielectric layer. The solubility of the metal oxide is enhanced by using H2O with a temperature higher than about 10° C. or a chemical with a temperature higher than about 15° C.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Shuang-Neng Peng, Chun-Hung Chen, Soon Huang, Weng-Liang Fang
  • Patent number: 6682659
    Abstract: A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: January 27, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Wen Cho, Kuwi-Jen Chang, Sen-Fu Chen, Kuang-Peng Lin, Shing-Jzy Tay, Szu-Hung Yang, Chai-Der Chang, Kuo-Su Huang, Jen-Shiang Leu, Weng-Liang Fang, Jyh-Ping Wang, Jow-Feng Lee
  • Patent number: 6543988
    Abstract: A wafer is carried on a blade supported on robotic arms. A plurality of guide clamps both move the wafer into a desired position on the blade and clamp the wafer in place during transport by the arms. The clamps are reciprocally mounted on the blade and are connected with and driven by a rotatable hub carried on the blade and rotated by the movement of the arms. Both the blade and the clamps include beveled surfaces that guide the wafer into place. The operation of the clamps is controlled by a laser that detects when the wafer is out of place or tilted on the blade.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: April 8, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Li Hsiao, Cheng-Chieh Hung, Yu-Tsung Fu, Weng-Liang Fang
  • Publication number: 20030017042
    Abstract: A wafer is carried on a blade supported on robotic arms. A plurality of guide clamps both move the wafer into a desired position on the blade and clamp the wafer in place during transport by the arms. The clamps are reciprocally mounted on the blade and are connected with and driven by a rotatable hub carried on the blade and rotated by the movement of the arms. Both the blade and the clamps include beveled surfaces that guide the wafer into place. The operation of the clamps is controlled by a laser that detects when the wafer is out of place or tilted on the blade.
    Type: Application
    Filed: July 18, 2001
    Publication date: January 23, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Li Hsiao, Cheng-Chieh Hung, Yu-Tsung Fu, Weng-Liang Fang
  • Patent number: 6124212
    Abstract: A method for forming a patterned polysilicon layer within a microelectronics fabrication. There is first provided a substrate layer employed within a microelectronics fabrication. There is then formed upon the substrate layer a blanket polysilicon layer. There is then formed upon the blanket polysilicon layer a blanket organic polymer layer. There is then formed upon the blanket organic polymer layer a patterned photoresist layer, where the patterned photoresist layer has a high areal density region and a low areal density region. There is then etched through a first plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket organic polymer layer to form a patterned organic polymer layer while reaching the blanket polysilicon layer.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: September 26, 2000
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Yuh-Da Fan, Weng-Liang Fang
  • Patent number: 5783482
    Abstract: A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: July 21, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Long Lee, Yeong-Rong Chang, Weng Liang Fang, Cheng-Hao Huang
  • Patent number: 5770523
    Abstract: A method is provided for the removal of the surface layer of the residual photoresist mask pattern used for metal subtractive etching which uses the same reactor equipment but employs reactive fluorine-containing gases to form volatile compounds with the surface layer, so that subsequently a conventional oxygen plasma stripping process can be used for complete resist residue removal without requiring excessive temperature exposure of the integrated circuit devices.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: June 23, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yeon Hung, Janet Yu, Weng-Liang Fang, Chang-Ching Kin
  • Patent number: 5747856
    Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric layer is formed on the surface of the source layer. The dielectric layer is patterned and etched forming a dielectric layer pattern with openings therein, a silicon epitaxial layer in the openings in the dielectric layer pattern. An N+ drain layer is formed on the surface of the silicon epitaxial layer. A second dielectric layer is formed on the surface of the device including the N+ drain layer. A conductor layer is formed and patterned containing silicon over the second dielectric layer. An N+ implant mask with an N+ opening over a region of the epitaxial layer is formed (source) and ion implanting through that N+ opening into the N+ implant mask in that region. A code implant mask over the conductor layer is formed and ions are implanted through the code implant mask into the device.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: May 5, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ling Chen, Sung-Mu Hsu, Weng Liang Fang