Abstract: A method of controlling work tasks for an artificial intelligence device includes the steps of: (a) receiving, by a receiving module, work task information, the work task information including a plurality of to-do tasks and a corresponding expected completion time frame, (b) retrieving, by a retrieval module, an execution number at which each of the to-do tasks is to be performed, and (c) determining, by a determination module, a first implementation number of execution times based on the work task information and the execution numbers, and determining a target task of each of the execution times, the target task is at least one of the to-do tasks.

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a to-be-processed base structure, where the to-be-processed base structure includes a base layer and pattern structures protruding from the base layer, and a surface of the base structure has adsorption groups; performing plasma treatment on the surface of the base structure by using a reaction gas, where the reaction gas chemically reacts with the adsorption group to cause quantities of precursor adsorption nucleation points on the surface of the base structure to tend to be same; and after the plasma treatment, forming, by using an atomic layer deposition (ALD) process, a target layer conformally covering the surface of the base structure.

Abstract: A method of controlling work tasks for an artificial intelligence device includes the steps of: (a) receiving, by a receiving module, work task information, the work task information including a plurality of to-do tasks and a corresponding expected completion time frame, (b) retrieving, by a retrieval module, an execution number at which each of the to-do tasks is to be performed, and (c) determining, by a determination module, a first implementation number of execution times based on the work task information and the execution numbers, and determining a target task of each of the execution times, the target task is at least one of the to-do tasks.

Abstract: A memristor with a two-dimensional (2D) material heterojunction and a preparation method thereof is provided. The memristor includes a substrate, a bottom electrode layer, a 2D material heterojunction layer and a top electrode layer from bottom to top. The 2D material heterojunction layer serves as an intermediate dielectric layer, and has a two-layer laminate structure composed of two different transitional metal dichalcogenides (TMDCs), with one layer in the laminate structure corresponding to one of the TMDCs. The present invention constructs a novel memristor totally based on 2D materials by improving the materials used for key functional layers in the device and the design for the overall structure of the device. Compared with the prior art, the present invention completely different from the conventional metal/insulator/metal (MIM) structure, and has advantages, such as lower operating voltage, excellent retention and switching stability.

Abstract: A photodiode for an image sensor and a method of fabricating the photodiode are disclosed. The photodiode includes a substrate having a surface defined as a light-incident surface of the photodiode, wherein a plurality of convex structures are provided on the light-incident surface of the photodiode, namely, a non-planar light-incident surface which is capable of reducing the light reflection and hence improving the ability of the photodiode to capture incident light, thereby enabling an image sensor that incorporates the photodiode to have a higher fill factor and a better performance.

Abstract: The present invention provides a method of forming semiconductor devices using SMT. The method comprises providing a substrate; depositing an SiO2 buffer film and a low tensile stress SiN film on the substrate; applying photoresist over the low tensile stress SiN film and exposing the low tensile stress SiN film on the NMOS region through photoresist exposure; applying UV radiation to the exposed low tensile stress SiN film; removing some hydrogen in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region; performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region; and removing the SiN film and the SiO2 buffer film. According to the method of forming semiconductor devices using SMT of the present invention, the conventional SMT is greatly simplified.

Abstract: A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.

Abstract: The invention relates to a method for fabricating copper interconnections in an ultra low dielectric constant film, comprising the following steps of: depositing an etching stop layer on a silicon wafer, depositing an ultra-low-k film on the etching stop layer, and depositing a SiO2-riched layer on the ultra-low-k film; forming a via and/or trench that penetrates through the SiO2-riched layer and the ultra-low-k film by using a photo-lithography and etching process; sputter-depositing a metal barrier layer and a copper seed crystal layer within the via and/or trench, performing a copper filling deposition by an electroplating process, performing a chemical mechanical polishing until the SiO2-riched layer is reached, whereby forming a copper interconnection layer.

Abstract: A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.

Abstract: A method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation comprises: step a: forming a protective layer on a semiconductor substrate; step b: forming trenches for isolating PMOS active regions and NMOS active regions on the semiconductor substrate and the protective layer; step c: forming a filling material layer in the trenches, so that the trenches are fully filled with the filling material layer to form shallow trench isolation structures. The advantageous is that, as for a device where a HARP process is applied to its shallow trench isolation, the stress in the STI can be tuned so as to be changed from tensile stress into compressive stress by performing ion implantation to the STI around the PMOS, therefore the stress state of the PMOS channel region may be changed and the performance thereof is improved.