Patents by Inventor Wenhong Sun
Wenhong Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947181Abstract: Provided is a focusing assembly including a focusing barrel and a barrel retaining ring; the focusing barrel includes a first sleeve, a second sleeve, and a third sleeve that are sequentially sleeved from inside to outside of the focusing barrel; the first sleeve is provided with a lens mounting portion for mounting a focusing lens, a first end of the second sleeve is provided with a display screen mounting portion for mounting a display screen, a second end of the second sleeve is detachably connected to the barrel retaining ring, the first end and the second end being opposite ends of the second sleeve; and the lens mounting portion and the display screen mounting portion are configured such that the relative position thereof in a focusing direction of the focusing assembly is adjustable.Type: GrantFiled: April 17, 2020Date of Patent: April 2, 2024Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yuhong Liu, Zhanshan Ma, Haoran Jing, Zheng Ge, Zhiyu Sun, Jinbao Peng, Hao Zhang, Wenhong Tian, Lili Chen
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Patent number: 10622515Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.Type: GrantFiled: May 25, 2018Date of Patent: April 14, 2020Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 10490697Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: June 28, 2018Date of Patent: November 26, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur, Brandon Robinson
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Patent number: 10460952Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.Type: GrantFiled: June 29, 2018Date of Patent: October 29, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
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Patent number: 10297460Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.Type: GrantFiled: April 25, 2017Date of Patent: May 21, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
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Patent number: 10211048Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.Type: GrantFiled: February 1, 2013Date of Patent: February 19, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Wenhong Sun, Rakesh Jain, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
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Patent number: 10199531Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.Type: GrantFiled: July 26, 2017Date of Patent: February 5, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 10199536Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.Type: GrantFiled: June 26, 2017Date of Patent: February 5, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Publication number: 20190019917Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: ApplicationFiled: June 28, 2018Publication date: January 17, 2019Applicant: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur, Brandon Robinson
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Patent number: 10181398Abstract: A solution for fabricating a group III nitride heterostructure and/or a corresponding device is provided. The heterostructure can include a nucleation layer, which can be grown on a lattice mismatched substrate using a set of nucleation layer growth parameters. An aluminum nitride layer can be grown on the nucleation layer using a set of aluminum nitride layer growth parameters. The respective growth parameters can be configured to result in a target type and level of strain in the aluminum nitride layer that is conducive for growth of additional heterostructure layers resulting in strains and strain energies not exceeding threshold values which can cause relaxation and/or dislocation formation.Type: GrantFiled: December 30, 2015Date of Patent: January 15, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Michael Shur, Remigijus Gaska
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Patent number: 10164147Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.Type: GrantFiled: July 28, 2017Date of Patent: December 25, 2018Assignee: Sensor Electronic Technology, Inc.Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Jinwei Yang, Michael Shur, Remigijus Gaska
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Patent number: 10158044Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: December 28, 2016Date of Patent: December 18, 2018Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
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Patent number: 10153396Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.Type: GrantFiled: December 29, 2017Date of Patent: December 11, 2018Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Publication number: 20180323071Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.Type: ApplicationFiled: June 29, 2018Publication date: November 8, 2018Applicant: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
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Publication number: 20180269355Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.Type: ApplicationFiled: May 25, 2018Publication date: September 20, 2018Applicant: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 10050175Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.Type: GrantFiled: October 30, 2017Date of Patent: August 14, 2018Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Publication number: 20180108806Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.Type: ApplicationFiled: December 29, 2017Publication date: April 19, 2018Applicant: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Publication number: 20180047870Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.Type: ApplicationFiled: October 30, 2017Publication date: February 15, 2018Applicant: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Publication number: 20170345968Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.Type: ApplicationFiled: July 28, 2017Publication date: November 30, 2017Applicant: Sensor Electronic Technology, Inc.Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Jinwei Yang, Michael Shur, Remigijus Gaska
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Patent number: 9831382Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: December 3, 2012Date of Patent: November 28, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur