Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, ?, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, ?, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, ?, z measurements with respect to the first r, ?, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, ?, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, ?, z coordinate system; and analyzing the second measurements with respect to the first measurements.

Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, ?, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, ?, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, ?, z measurements with respect to the first r, ?, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, ?, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, ?, z coordinate system; and analyzing the second measurements with respect to the first measurements.

Abstract: A waferless seasoning process is described, which waferless seasoning process is suitable for an etching chamber of an etching machine when the etching environment is so bad that etching cannot be performed. A dry cleaning process with a plasma formed by oxygen and hydrogen bromide is performed to restore the etching environment in the etching chamber.

Abstract: A method of fabricating a MOS transistor. A substrate has a gate formed thereon and a LDD is formed in the substrate beside the gate. A spacer is formed on the sidewall of the gate. A sacrificial layer is formed over the substrate to cover the gate and the spacer. A portion of the sacrificial layer is removed to expose a portion of the spacer. The exposed spacer is removed, such that a portion of the gate sidewall is exposed. The sacrificial layer is removed. A source/drain region is then formed in the substrate beside the spacer.

Abstract: A fabrication method for a gate spacer. The method comprises provision of a substrate with a gate formed thereon, after which a SiNx spacer is formed on the gate sidewall. The substrate is then covered with a SiOx layer. A part of the SiOx layer is removed until the surface of the SiOx layer is lower than the top surface of the gate. A portion of the SiNx layer is removed to expose the top edge of the gate spacer and to increase the exposed area of the gate. The SiOx layer is consequently removed.