Abstract: A superconducting eddy-current brake for high-speed trains includes a pair of superconducting magnet units with alternate arrangement of N and S poles; and a cryogenic system. The superconducting magnet units are fixed on a bottom of a bogie of the train and an air gap is provided between the superconducting magnet units and a top surface of a rail below the bogie. The cryogenic system is provided on the bogie of the train. Each superconducting magnet unit is embedded with a superconducting container including a coil case, a thermal shield and a Dewar successively from inside to outside. The coil case is filled with liquid helium. A superconducting coil is provided in the coil case and immersed in the liquid helium. A high-vacuum environment is provided in the thermal shield. Liquid nitrogen inlet and outlet pipes are provided on an outer wall of the thermal shield.

Abstract: A superconducting magnet for eddy-current braking for a high-speed train. The superconducting magnet is fixed at a bottom of a bogie of the high-speed train through a connecting mechanism, and an air gap is formed between the superconducting magnet and a top of a guide rail below the bogie. The superconducting magnet after being excited generates an eddy-current effect with the guide rail of the high-speed train, so as to generate a braking force opposite to a traveling direction of the train, thereby braking the high-speed train. A liquid-level meter is provided on the superconducting magnet to detect a position of a cooling agent liquid level in real time. The superconducting magnet withstands vibration impact through elastic tie rod assemblies when the high-speed train is under operation, showing good adaptability.

Abstract: A superconducting eddy-current brake for high-speed trains includes a pair of superconducting magnet units with alternate arrangement of N and S poles; and a cryogenic system. The superconducting magnet units are fixed on a bottom of a bogie of the train and an air gap is provided between the superconducting magnet units and a top surface of a rail below the bogie. The cryogenic system is provided on the bogie of the train. Each superconducting magnet unit is embedded with a superconducting container including a coil case, a thermal shield and a Dewar successively from inside to outside. The coil case is filled with liquid helium. A superconducting coil is provided in the coil case and immersed in the liquid helium. A high-vacuum environment is provided in the thermal shield. Liquid nitrogen inlet and outlet pipes are provided on an outer wall of the thermal shield.

Abstract: A superconducting magnet for eddy-current braking for a high-speed train. The superconducting magnet is fixed at a bottom of a bogie of the high-speed train through a connecting mechanism, and an air gap is formed between the superconducting magnet and a top of a guide rail below the bogie. The superconducting magnet after being excited generates an eddy-current effect with the guide rail of the high-speed train, so as to generate a braking force opposite to a traveling direction of the train, thereby braking the high-speed train. A liquid-level meter is provided on the superconducting magnet to detect a position of a cooling agent liquid level in real time. The superconducting magnet withstands vibration impact through elastic tie rod assemblies when the high-speed train is under operation, showing good adaptability.

Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.

Abstract: An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.

Abstract: A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.