Patents by Inventor Wenhua W. Yang
Wenhua W. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11329660Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.Type: GrantFiled: February 15, 2021Date of Patent: May 10, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Hajime Shibata, Gerard E. Taylor, Wenhua W. Yang
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Publication number: 20210167790Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.Type: ApplicationFiled: February 15, 2021Publication date: June 3, 2021Applicant: Analog Devices International Unlimited CompanyInventors: Hajime SHIBATA, Gerard E. TAYLOR, Wenhua W. YANG
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Patent number: 10924128Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.Type: GrantFiled: May 24, 2019Date of Patent: February 16, 2021Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Hajime Shibata, Gerard E. Taylor, Wenhua W. Yang
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Publication number: 20200373934Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Applicant: Analog Devices International Unlimited CompanyInventors: Hajime SHIBATA, Gerard E. TAYLOR, Wenhua W. YANG
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Patent number: 10727853Abstract: A DAC has a plurality DAC cells, and timing mismatch among the DAC cells can introduce errors in an output of a DAC. An efficient technique can be implemented to extract the timing error of a DAC cell. The technique involves a mixer to mix the timing error to DC (DC stands for direct current, where signal frequency is zero) and a VCO ADC to observe the output of the DAC cell to measure and extract the timing error. A first measurement is made using a first quadrature phase signal and a second measurement is made using a second quadrature phase signal. A difference between the first measurement and the second measurement yields the timing error of the DAC cell. Advantageously, the mixer can be integrated within a voltage-to-current converter of the VCO ADC. The timing error can be corrected in the digital domain or analog domain.Type: GrantFiled: June 6, 2019Date of Patent: July 28, 2020Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Jialin Zhao, Matthew Louis Courcy, Wenhua W. Yang, Gerard E. Taylor
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Patent number: 10579086Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.Type: GrantFiled: August 13, 2018Date of Patent: March 3, 2020Assignee: Analog Devices, Inc.Inventors: Haiyang Zhu, Wenhua W. Yang, Nathan T. Egan
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Publication number: 20180348806Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.Type: ApplicationFiled: August 13, 2018Publication date: December 6, 2018Applicant: Analog Devices, Inc.Inventors: Haiyang ZHU, Wenhua W. YANG, Nathan T. EGAN
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Patent number: 10048714Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.Type: GrantFiled: January 31, 2014Date of Patent: August 14, 2018Assignee: ANALOG DEVICES, INC.Inventors: Haiyang Zhu, Wenhua W. Yang, Nathan T. Egan
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Patent number: 9843337Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.Type: GrantFiled: March 16, 2017Date of Patent: December 12, 2017Assignee: ANALOG DEVICES GLOBALInventors: Zhao Li, Trevor Clifford Caldwell, David Nelson Alldred, Yunzhi Dong, Prawal Man Shrestha, Jialin Zhao, Hajime Shibata, Victor Kozlov, Richard E. Schreier, Wenhua W. Yang
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Patent number: 9768793Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.Type: GrantFiled: November 30, 2016Date of Patent: September 19, 2017Assignee: ANALOG DEVICES GLOBALInventors: Qingdong Meng, Hajime Shibata, Richard E. Schreier, Martin Steven McCormick, Yunzhi Dong, Jose Barreiro Silva, Jialin Zhao, Donald W. Paterson, Wenhua W. Yang
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Patent number: 9762221Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.Type: GrantFiled: June 14, 2016Date of Patent: September 12, 2017Assignee: ANALOG DEVICES GLOBALInventors: Yunzhi Dong, Victor Kozlov, Wenhua W. Yang, Trevor Clifford Caldwell, Hajime Shibata
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Publication number: 20170179969Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.Type: ApplicationFiled: November 30, 2016Publication date: June 22, 2017Applicant: ANALOG DEVICES GLOBALInventors: Qingdong Meng, Hajime Shibata, Richard E. Schreier, Martin Steven McCormick, Yunzhi Dong, Jose Barreiro Silva, Jialin Zhao, Donald W. Paterson, Wenhua W. Yang
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Patent number: 9543974Abstract: In some converter architectures, unary digital-to-analog (DAC) converter elements generate an analog output which represents the digital input signal. Thermometer codes trigger an appropriate number of DAC elements to generate the analog output. The DAC elements are not all perfectly weighted, and mismatch shaping is often used to dynamically equalize the usage of each DAC element during data conversion to average out the mismatches. Unfortunately, mismatch shaping adds additional switching and can worsen the effect of switching errors. Switching errors which are non-linearly dependent on the input causes a second order distortion if the sum of the switching errors corresponding to a set of DAC elements is not zero. Prior to data conversion, calibration can select a subset of DAC elements having a lesser sum of switching errors for data conversion. Other (redundant) DAC elements are not used at all or shut off permanently.Type: GrantFiled: September 18, 2015Date of Patent: January 10, 2017Assignee: Analog Devices, Inc.Inventor: Wenhua W. Yang
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Publication number: 20160373101Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.Type: ApplicationFiled: June 14, 2016Publication date: December 22, 2016Inventors: Yunzhi Dong, VICTOR KOZLOV, WENHUA W. YANG, TREVOR CLIFFORD CALDWELL, HAJIME SHIBATA
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Patent number: 9425816Abstract: Data converters convert signals in analog form to digital form or from digital form to analog form. Due to mismatches between devices that are intended to be identical (unary elements), some data converters outputs may have undesirable characteristics, such as non-linearities. Shuffling the inputs to the unary elements based on a pseudo-random sequence is a technique that can average out the mismatches over time. However, shuffling generally requires a complex switch matrix, and can potentially impact the speed of the converter. To address mismatches, a high speed technique for rotating comparator thresholds is implemented to effectively rotate an array of unary digital-to-analog converter elements. The technique is particularly advantageous for addressing mismatches in unary digital-to-analog converters used for reconstructing a quantized analog signal within delta-sigma analog-to-digital converter.Type: GrantFiled: June 3, 2015Date of Patent: August 23, 2016Assignee: Analog Devices GlobalInventors: Wenhua W. Yang, Richard E. Schreier
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Patent number: 9350371Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.Type: GrantFiled: December 15, 2014Date of Patent: May 24, 2016Assignee: Analog Devices GlobalInventors: Trevor Clifford Caldwell, Richard E. Schreier, David Alldred, Wenhua W. Yang
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Patent number: 9231614Abstract: The present disclosure describes a mechanism to digitally correct for the static mismatch of the digital-to-analog converter (DAC) in at least the first-stage of a multi-stage noise shaping (MASH) analog-to-digital converter (ADC). The correction is applicable to continuous-time implementations, and is especially attractive for high-speed applications.Type: GrantFiled: June 6, 2014Date of Patent: January 5, 2016Assignee: Analog Devices, Inc.Inventors: Jose Barreiro Silva, Jialin Zhao, Wenhua W. Yang
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Patent number: 9203426Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).Type: GrantFiled: June 11, 2014Date of Patent: December 1, 2015Assignee: ANALOG DEVICES GLOBALInventors: Jialin Zhao, Richard E. Schreier, Jose Barreiro Silva, Hajime Shibata, Wenhua W. Yang, Yunzhi Dong
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Patent number: 9178529Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.Type: GrantFiled: October 18, 2013Date of Patent: November 3, 2015Assignee: Analog Devices GlobalInventors: Yunzhi Dong, Hajime Shibata, Wenhua W. Yang, Richard E. Schreier
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Publication number: 20150288380Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).Type: ApplicationFiled: June 11, 2014Publication date: October 8, 2015Applicant: ANALOG DEVICES TECHNOLOGYInventors: JIALIN ZHAO, RICHARD E. SCHREIER, JOSE BARREIRO SILVA, HAJIME SHIBATA, WENHUA W. YANG, YUNZHI DONG