Abstract: A programmable delay-line circuit is provided that includes a single ring oscillator that is calibrated continuously by a calibration logic circuit. A clock edge sampler samples an input clock responsive to a plurality of oscillator output signals from the ring oscillator to form a corresponding plurality of data output signals. A clock edge voter processes the data output signals to identify a first one of the oscillator output signals that samples an edge transition of the input clock. Based upon a desired delay, a decoder selects for a second one of the oscillator output signals to produce an output clock signal.

Abstract: A vulcanizing agent is added during the processing of a polymer, and can form a crosslinking structure network in the polymer, thereby improving the mechanical properties of the material. Furthermore, the crosslinking agent can also de-crosslink the polymer material at a high temperature, and after being cooled, same can be crosslinked again to produce a network structure, thus endowing the polymer material with thermoplasticity for repeated processing.

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

Abstract: A rice white leaf and panicle gene wlp3 is provided. The cDNA sequence of the white leaf and panicle gene wlp3 is shown in SEQ ID NO: 1, and the encoded amino acid sequence of the protein is shown in SEQ ID NO: 2. The rice white leaf and panicle gene wlp3 is applied to rice stress resistance and yield increase. The white leaf and panicle gene wlp3 is configured to improve cold tolerance of plants, enhance photosynthetic rate, increase plant height, leaf albinism at seedling stage, panicle albinism at heading stage, and increase panicle length at low temperature. The present disclosure obtains the rice white leaf and panicle gene wlp3 through screening and mutagenesis, which is related to the stress resistance and chlorophyll synthesis of rice. Therefore, the present disclosure provides a foundation for rice breeding.

Abstract: A low-voltage differential signaling receiver is provided that amplifies a differential input voltage to produce a differential output voltage. A signal distortion circuit that detects a distortion in a differential output voltage to assert a signal detection signal that adjusts a gate voltage of a pair of load transistors to reduce the distortion. The load transistors are selectively diode connected to reduce power consumption.

Abstract: A low-voltage differential signaling receiver is provided that amplifies a differential input voltage to produce a differential output voltage. A signal distortion circuit that detects a distortion in a differential output voltage to assert a signal detection signal that adjusts a gate voltage of a pair of load transistors to reduce the distortion. The load transistors are selectively diode connected to reduce power consumption.

Abstract: Embodiments of this application provide a method and apparatus, a terminal and a medium. The method includes the following steps. A target terminal displays, in a video session, a video session interface including an image display region for displaying images associated with one or more users participating in the video session. The target terminal displays a target virtual image of a user of the target terminal in the image display region. The target terminal acquires movement information of the user and controls the target virtual image displayed in the image display region to perform a target interaction action corresponding to the movement information of the user. Finally, the target terminal transmits movement data of the target virtual image performing the target interaction action, to terminals of the other users of the video session to render the target virtual image to perform the target interaction action on the corresponding terminals.

Abstract: A vulcanizing agent is added during the processing of a polymer, and can form a crosslinking structure network in the polymer, thereby improving the mechanical properties of the material. Furthermore, the crosslinking agent can also de-crosslink the polymer material at a high temperature, and after being cooled, same can be crosslinked again to produce a network structure, thus endowing the polymer material with thermoplasticity for repeated processing.

Abstract: A combined lifting burn fencing equipment is disclosed herein. The combined lifting barn fencing equipment includes a barn movably mounted in a first annular groove in the periphery of stage, a lifting mechanism that drives the barn to lift up and down, a fence movably mounted in a second annular groove of the barn, and a hoisting mechanism that drives the fence to lift up and down. The lifting mechanism is mounted at the bottom of the first annular groove. The hoisting mechanism is mounted at the top of the gate above the stage. The barn is mounted a bedplate. The barn descends to the first annular groove or rises to the above of the stage driven by the lifting mechanism.

Abstract: A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.

Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

Abstract: A hybrid pulse-width control circuit is provided that includes a ramp voltage generator for generating a ramp voltage signal. A clock pulse generator asserts an output clock signal responsive to the ramp voltage signal equaling a reference voltage.

Abstract: A switched-capacitor voltage divider is provided that functions to divide an input voltage only while a low-duty-cycle clock pulse signal is asserted. All the switches in the switched-capacitor voltage divider are idle during an off time for the low-duty-cycle clock pulse signal.

Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

Abstract: An embedded integrated lifting rotation table which comprises a lifting table and a rotation table which is embedded in the lifting table is disclosed. At least a group of rotating driving devices are installed on the lifting table to drive the rotation table to rotate. There are two lifting tables at least, each lifting table connects with a group of single lifting driving devices. The rotation table comprises at least two rotation table components joint together. The quantity of the rotation table components equals to the quantity of the lifting tables. Each lifting table is embedded with a rotation table component. The first locking device is installed between two adjacent rotation table components. The second locking device is installed between the lifting table and the rotation table components which is embedded in the lifting table.

Abstract: An embedded integrated lifting rotation table which comprises a lifting table and a rotation table which is embedded in the lifting table is disclosed. At least a group of rotating driving devices are installed on the lifting table to drive the rotation table to rotate. There are two lifting tables at least, each lifting table connects with a group of single lifting driving devices. The rotation table comprises at least two rotation table components joint together. The quantity of the rotation table components equals to the quantity of the lifting tables. Each lifting table is embedded with a rotation table component. The first locking device is installed between two adjacent rotation table components. The second locking device is installed between the lifting table and the rotation table components which is embedded in the lifting table.

Abstract: A combined lifting burn fencing equipment is disclosed herein. The combined lifting barn fencing equipment includes a barn movably mounted in a first annular groove in the periphery of stage, a lifting mechanism that drives the barn to lift up and down, a fence movably mounted in a second annular groove of the barn, and a hoisting mechanism that drives the fence to lift up and down. The lifting mechanism is mounted at the bottom of the first annular groove. The hoisting mechanism is mounted at the top of the gate above the stage. The barn is mounted a bedplate. The barn descends to the first annular groove or rises to the above of the stage driven by the lifting mechanism.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SC-CMFB circuit.

Abstract: Certain aspects of the present disclosure provide a high-speed AC-coupled inverter-based buffer, which may be used as a buffer for a voltage-controlled oscillator (VCO), for example. One example buffer for a VCO generally includes a first inverter stage having an input node configured to receive a first complementary signal of a differential pair, a second inverter stage having an input node configured to receive a second complementary signal of the differential pair, a biasing stage replicating the first inverter stage or the second inverter stage, wherein an output node of the biasing stage is connected with an input node of the biasing stage, a first impedance coupled between the input node of the first inverter stage and the input node of the biasing stage, and a second impedance coupled between the input node of the second inverter stage and the input node of the biasing stage.