Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

Abstract: A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

Abstract: An FFT-IFFT-based anomalous point detection method with valid check is disclosed, which includes: if a difference between data indicated by a point on an original time series and data indicated by a corresponding point on a first time series, that is obtained by applying FFT, high frequency filtering, and IFFT to the original time series, is greater than a first preset threshold, performing interpolation on the point on the original time series to obtain a second time series; applying the FFT, the high frequency filtering, and the IFFT to the second time series to obtain a third time series; and determining the point on the original time series as an anomalous point of the original time series, if a difference between the data indicated by the point on the original time series and data indicated by a corresponding point on the third time series is greater than the first preset threshold.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module, configured to read data in a storage unit on a bit line or a storage unit on a reference bit line; and a first switch module, configured to control the amplification module to be disconnected from the reference bit line when the sense amplifier reads a first state for the bit line and the sense amplifier is in an amplification stage, and control the amplification module to be connected to the reference bit line when the sense amplifier reads a second state for the bit line and the sense amplifier is in the amplification stage. The present disclosure can reduce the power consumption of the sense amplifier.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

Abstract: A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: A support apparatus for use in civil construction includes a base (1), hydraulic support rods (2) installed at four corners on the bottom of the base (1), a pulley (3) installed at an inner side of the hydraulic support rods (2), a first motor (5) installed at the bottom of the base (1), a transmission wheel (6) provided in the middle portion of a transmission shaft (4), threaded rods (7) disposed at two ends of the transmission shaft (4). A hydraulic cylinder (9) is installed at the top of the base (1). A hydraulic station (10) is installed at a side of the hydraulic cylinder (9), and a support base (11) is fixed on the top of the hydraulic cylinder (9). A second motor (12) is installed at an end of the support base (11), and a lead screw (18) is installed inside the support base (11) at the center.

Abstract: A civil engineering anti-seismic structure includes a base. A fixing structure is fixedly welded at the bottom center of the base. A through-hole is provided at the top center of the base. Sliding grooves are provided on corresponding inner walls at two sides of the base. Sliding blocks are slidably connected to the sliding grooves inside the grooves and are symmetrically installed at two sides of a sliding plate. A top block is fixedly welded at the top center of the sliding plate (8), and a fixing groove is provided at the top center of the top block. A shock-absorbing damping pad is fixedly adhered to a bottom inner wall of the base. A first limiting plate is fixedly welded around the top portion of the sliding plate, and a second limiting plate is fixedly welded around the through-hole at a top inner wall of the base.