Abstract: A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

Abstract: The technology of this disclosure relates to a chip packaging apparatus. The chip packaging apparatus includes a first differential pin pair, a first pin, and a second pin. The first differential pin pair includes a first differential signal pin and a second differential signal pin. In addition, the first pin and the second pin are both located between the first differential signal pin and the second differential signal pin, and the first pin and the second pin are differential signal pins (or both are power pins). The first pin is adjacent to the first differential signal pin and the second differential signal pin. The second pin is adjacent to the first differential signal pin and the second differential signal pin. The first pin and the second pin are respectively located on two sides of a first imaginary straight line connecting the first differential signal pin to the second differential signal pin.