Abstract: A food processor for processing food stuffs having a base assembly, a jar assembly, and a blade assembly that can be rotated from a use position to a stored position is disclosed. The food processor includes a lid that is connected to the jar assembly by a hinge and closed by use of a latch. The jar assembly is connected to the base assembly by the use of push pins on the base assembly which engage corresponding holes on the jar assembly.

Abstract: A voltage regulator system includes a switch system including a power switch to conduct an output current through an inductor based on an input voltage and a switching signal to generate an output voltage at a load. A feedback system generates a PWM signal based on the output voltage and based on a variable reference voltage. A gate driver system generates the switching signal based on the PWM signal. The gate driver system controls the switch system to increase the output voltage at output voltage slopes in each of startup stages during startup of the voltage regulator system. A sampling system samples the output current and the output voltage during the startup of the voltage regulator system to measure each slope of the output voltage slopes at each of the respective startup stages during the startup of the voltage regulator system.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for regulated hybrid converters. An example apparatus includes an input terminal; an output terminal, a first converter circuit coupled between the input terminal and an intermediate node, the first converter circuit having a first switch node, a second converter circuit coupled between the intermediate node and the output terminal, the second converter circuit having a second switch node; a first inductor coupled between the first switch node and the second switch node, and a second inductor coupled between the second switch node and the output terminal.

Abstract: A circuit includes a phase control logic, an analog-to-digital converter (ADC), and digital logic. The phase control logic is configured to couple to a plurality of power phases of a multi-phase power supply. The digital logic is configured to couple to the phase control logic and the ADC, to receive an instruction to operate in a self-calibration mode of operation, receive a first message including a value associated with a calibrated load configured to couple to the plurality of power phases, perform a self-calibration sub-routine for each power phase of the plurality of power phases based at least partially on the received instruction, the received first message, and a signal received from the ADC, and receive a second message instructing the digital logic to store a result of the self-calibration in a memory of the circuit.

Abstract: An apparatus includes first and second power converter stages, each stage having a primary side and a secondary side. The primary side of the first stage includes a switch T1A coupled to a voltage source and a switch T3A coupled to the switch T1A. The primary side of the second stage includes a switch T2A coupled to the switch T3A and a switch T4A coupled to the switch T3A and to the voltage source. The apparatus includes a control circuit to control an on/off time of the switches. The control circuit includes four gate driver controllers to control the on/off time of the switches and a current sharing control section to increase or decrease the on time of a switch based on a comparison of a current through one of multiple output inductors to an average current through the multiple output inductors.

Abstract: A circuit for a multi-phase power regulator including a power stage with a first phase and a second phase, the circuit including phase management circuitry coupled to the first phase and the second phase to control the first phase and the second phase, a first comparator coupled to an output of the multi-phase power regulator to compare a value of the output of the multi-phase power regulator to a first threshold value to produce a first comparison result, and phase shedding circuitry coupled to the first comparator and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result.