Abstract: Devices and methods for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

Abstract: High frames-per-second (FPS) displays are becoming more ubiquitous in devices such as smartphones, laptops, etc. For displaying data on displays, render sync signal and compose sync signal control timings of rendering and composing. Conventionally, there is one render sync signal and one compose sync signal for a display, and both share the same frequency as the HW sync signal of the display hardware. As the FPS of the display becomes faster and faster, i.e., as HW sync signal frequency increases, some application layers may be unable to render fast enough to keep up with the increased frequency. To address this issue, it is proposed to provide multiple render sync signals of differing frequencies and phases, and different render sync signals may be used to control the timings of rendering of different application layers. Through such managing of the application layer rendering, a better user experience can be provided.

Abstract: The present disclosure relates to methods and devices for display processing including an apparatus, e.g., a display processor. In some aspects, the apparatus may store one or more pixel conversion factors for at least one display panel. The apparatus may also determine whether to switch from a previous frame refresh rate to an updated frame refresh rate at the at least one display panel. Additionally, the apparatus may identify, upon determining to switch from the previous frame refresh rate to the updated frame refresh rate, a pixel conversion factor of the one or more pixel conversion factors associated with the updated frame refresh rate. The apparatus may also refresh the at least one display panel based on the updated frame refresh rate associated the pixel conversion factor.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing a plurality of layers of image data corresponding to a frame configured to be displayed on a display, the plurality of layers comprising a first subset of layers having respective bit-depths less than or equal to a threshold and a second subset of layers having respective bit-depths greater than the threshold. The method includes performing, by a first processor, composition processing of at least one first layer of the first subset of layers based on the at least one first layer having a respective bit-depth less than or equal to the threshold. The method further includes performing, by a second processor, composition processing of at least one second layer of the second subset of layers based on the at least one second layer having a respective bit-depth greater than the threshold.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.