Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first user definable number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first user definable number of clock cycles; a second counter for testing the identified activated key for a first user definable number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first user definable number of hardware key scan cycles.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: A method for debugging a read only memory (ROM) in a wireless target device is disclosed. A wireless communication link is established between the target device and a host computer. A debug mode change command is received from the host computer by the application program running on the target device via a wireless communication interface in the target device. The wireless communication interface is parsed with the monitor program. A debug instruction is received by the monitor program from a debugger in the host computer where the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location. An acknowledgement is transmitted from the target device to the debugger in the host computer, and, in response to the acknowledgement, a second debug instruction is received from the debugger in the host computer.

Abstract: An apparatus for tracking a real time clock comprising a delay element for receiving a first clock signal and providing a second delayed clock signal, a quadrature interface including a first input and a second input for respectively receiving the first and second clock signals, control logic adapted to provide a state machine including four states, the four states respectively corresponding to a 2-bit gray code such that a current state is selected by determining a correspondence of the first and second inputs to the 2-bit gray code and a counter is incremented upon a transition between a first state and a second state of the state machine.

Abstract: According to one embodiment, a system with a multi-purpose switch for providing a power on function and other functions to a user comprises a temporary power control circuit configured to be coupled to and decoupled from a power source by the multi-purpose switch. The system also comprises a continuous power control circuit to provide continuous power. As a result, the multi-purpose switch is capable of providing other functions when the continuous power is being provided. In one embodiment, a method for utilizing a multi-purpose switch to provide a power on function and other functions to a user comprises coupling a temporary power control circuit to a power source by the multi-purpose switch, triggering a continuous power control circuit to provide continuous power, decoupling the temporary power control circuit from the power source by the multi-purpose switch, and making the multi-purpose switch available to provide other functions.

Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first user definable number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first user definable number of clock cycles; a second counter for testing the identified activated key for a first user definable number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first user definable number of hardware key scan cycles.

Abstract: According to one embodiment, a system with a multi-purpose switch for providing a power on function and other functions to a user comprises a temporary power control circuit configured to be coupled to and decoupled from a power source by the multi-purpose switch. The system also comprises a continuous power control circuit to provide continuous power. As a result, the multi-purpose switch is capable of providing other functions when the continuous power is being provided. In one embodiment, a method for utilizing a multi-purpose switch to provide a power on function and other functions to a user comprises coupling a temporary power control circuit to a power source by the multi-purpose switch, triggering a continuous power control circuit to provide continuous power, decoupling the temporary power control circuit from the power source by the multi-purpose switch, and making the multi-purpose switch available to provide other functions.

Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first predetermined number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first predetermined number of clock cycles; a second counter for testing the identified activated key for a first predetermined number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first predetermined number of hardware key scan cycles.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: A polyphase filter including M taps, each of the M taps including a filter coefficient. The filter also includes a multiplier-accumulator (MAC) shared by the M taps, a plurality of multiplexors for sequentially selecting a subset of the plurality of taps, and a scheduler for controlling the MAC to perform arithmetic operations on respective filter coefficients of the selected subset of the plurality of taps.

Abstract: A method and apparatus are disclosed for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of key-scan logic can be tested by the GPIO interface by temporarily disconnecting the outputs of the various rows and columns and substituting signals generated by a test algorithm into the input terminals of the key-scan logic. The test signal is processed by the key scan circuitry and a key-scan output signal is generated. This key-scan output signal is then compared to a known reference output signal to determine if the key-scan logic and associated circuitry is operating properly. Other embodiments of the GPIO testing system can be used to test other user devices such as a computer mouse/scrolling device.

Abstract: An apparatus for tracking a real time clock comprising a delay element for receiving a first clock signal and providing a second delayed clock signal, a quadrature interface including a first input and a second input for respectively receiving the first and second clock signals, control logic adapted to provide a state machine including four states, the four states respectively corresponding to a 2-bit gray code such that a current state is selected by determining a correspondence of the first and second inputs to the 2-bit gray code and a counter is incremented upon a transition between a first state and a second state of the state machine.

Abstract: A method for debugging a read only memory (ROM) in a wireless target device is disclosed. A wireless communication link is established between the target device and a host computer. A debug mode change command is received from the host computer by the application program running on the target device via a wireless communication interface in the target device. The wireless communication interface is parsed with the monitor program. A debug instruction is received by the monitor program from a debugger in the host computer where the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location. An acknowledgement is transmitted from the target device to the debugger in the host computer, and, in response to the acknowledgement, a second debug instruction is received from the debugger in the host computer.

Abstract: A method for debugging a ROM in a wireless target device. After a wireless communication link is established with the target device by a host computer, a debug mode change command is transmitted to the target device by the host computer. The debug mode change command is received by the target device and a monitor program is enabled to parse the serial port. A debug instruction from a debugger in the host computer is then received by the monitor program where, the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location in the application program. An acknowledgement package is transmitted to the debugger in the host computer, and a second debug instruction is received from the debugger, responsive to the acknowledgement package.

Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first predetermined number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first predetermined number of clock cycles; a second counter for testing the identified activated key for a first predetermined number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first predetermined number of hardware key scan cycles.

Abstract: A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a wireless user interface device and a wirelessly enabled host is generated by calculating a modulo solution for an input variable. In some embodiments of the invention, the communication between the user input device and the wirelessly enabled host complies with the Bluetooth wireless communication standard. For the embodiments of the present invention relating to communications systems implementing the Bluetooth standard, a method and apparatus is disclosed for generating communication frequencies based on modulo 23 and modulo 79 solutions input variables. The method and apparatus of the present invention can generate the communication frequency with a minimum number of calculations using simple binary addition, as opposed to prior art methods that generally require numerous iterations and complex calculations.