Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.

Abstract: The present disclosure relates to the field of fingerprint recognition technologies, and provides a fingerprint recognition apparatus and a manufacturing method therefor, a mobile terminal, and a fingerprint lock. The apparatus includes: a substrate defining a protrusion on a surface of the substrate; a fingerprint chip, including: a signal processing circuit connected to the protrusion by passing through a TSV structure, a plurality of sensing electrodes connected to the signal processing circuit, and a protection layer covering the plurality of sensing electrodes; and a touch cover plate located on the protection layer.

Abstract: The present disclosure relates to the field of fingerprint recognition technologies, and provides a fingerprint recognition apparatus and a manufacturing method therefor, a mobile terminal, and a fingerprint lock. The apparatus includes: a substrate defining a protrusion on a surface of the substrate; a fingerprint chip, including: a signal processing circuit connected to the protrusion by passing through a TSV structure, a plurality of sensing electrodes connected to the signal processing circuit, and a protection layer covering the plurality of sensing electrodes; and a touch cover plate located on the protection layer.

Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.

Abstract: A method for preventing wafer edge peeling in a metal wiring process. A buffer layer is formed between a diffusion barrier layer of a metal wiring substructure and a semiconductor substrate. The buffer layer is an insulating dielectric layer, preferably a silicon oxide layer, or a polysilicon layer. The silicon oxide layer is formed in a process for forming a Shallow Trench Isolation (STI) structure. Using the above processes, the structure of direct contact between the diffusion barrier layer of the metal wiring structure and the semiconductor substrate can be avoided, and hence wafer edge peeling can be avoided without any modification to a conventional semiconductor fabrication procedure and with low cost and improved operability. This method is applicable to various semiconductor fabrication processes.