Patents by Inventor Wenliang Dai
Wenliang Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240193333Abstract: A multilevel distributed parallel computing method for integrated circuit board simulation, belonging to the technical field of integrated circuit simulation, includes following steps: S100, calculating number of nodes; S200, allocating tasks; S300, calculating and solving; and S40, judging convergence. By dynamically paralleling multiple computers, the present invention can maximize utilization of computing resources, improve simulation efficiency, and finally achieve a purpose of shortening design cycle. And in the simulation process, through the dynamic result analysis method, frequency points that need to be solved can be actually found, and accurate full-band results with the least number of solutions is completed.Type: ApplicationFiled: September 6, 2022Publication date: June 13, 2024Inventors: Wenliang DAI, Liguo JIANG, Feng LING, Jian ZHANG
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Publication number: 20240160858Abstract: Embodiments described herein provide a method of generating a vision-language task output to a text instruction relating to an input image, the method comprising receiving, via a data interface, the input image and the text instruction comprising an instruction relating to the image. The method further includes encoding, via an image encoder, the image into a first image representation. The method further includes generating, by a multimodal encoder, a second image representation based on cross-attending the first image representation to the text instruction. The method further includes generating, by a neural network based language model, a vision-language task output in response to the text instruction based on an input combining the second image representation and the text instruction.Type: ApplicationFiled: November 9, 2023Publication date: May 16, 2024Inventors: Wenliang Dai, Junnan Li, Chu Hong Hoi, Dongxu Li
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Publication number: 20230409531Abstract: A method for real-time extraction of on-chip simulation information including acquiring simulation job information, and analyzing the simulation job information to obtain option and parameter information; and acquiring index information from a simulation project according to the option and the parameter information, and formatting the index information to obtain a simulation result. According to said method, key information of a simulation result is extracted in real time by performing text scanning and pattern analysis on a log file during a simulation process, so that a user can conveniently learn about the progress situation of the current simulation task at any time, and determine to continue or terminate the task at any time according to the current state and result situation, thereby more flexibly controlling a flow according to an actual situation, simplifying operations, increasing design efficiency, and compensating for the disadvantages of traditional simulation methods.Type: ApplicationFiled: March 17, 2021Publication date: December 21, 2023Inventors: Liguo JIANG, Feng LING, Yeliang TANG, Wenliang DAI
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Publication number: 20230385492Abstract: A method for reconstructing physical connection relationships of general EDA model layouts comprising: separately establishing interconnection relationships between stack layers in an EDA model, connection relationships of graphics on each stack layer, and connection relationships of graphics on interconnected stack layers; summarizing the connection relationships established, and then establishing connection relationships of all graphics of an overall EDA model; and separately establishing physical connection relationships of interconnected graphics in each group to obtain physical connection relationships of the overall EDA model layout.Type: ApplicationFiled: March 16, 2021Publication date: November 30, 2023Inventors: Yunzhu DU, Feng LING, Wenliang DAI, Liguo JIANG, Yan LV, Zhichao GU
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Publication number: 20230297342Abstract: In a method for developing a child application, an interface of a child application developer tool is displayed. The child application developer tool is configured to provide a plurality of child application development modes. Each of the child application development modes is associated with a different run-time environment. A user selection of one of the plurality of child application development modes is received via the interface. Based on the selected one of the plurality of child application development modes, development mode information of a parent application that is associated with the one of the plurality of child application development modes is obtained. The run-time environment of the parent application is created based on the obtained application development mode information. At least one of code editing or code debugging of the child application is performed via the child application developer tool.Type: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Wenliang DAI, Canhui HUANG
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Patent number: 11726749Abstract: This disclosure includes a child application development method. In the method, an interface of a child application developer tool is displayed. The child application developer tool is a native child application developer tool of a first parent application that is configured with an extension corresponding to development processing for a child application of a second parent application. A development instruction for the child application of the second parent application is received via the interface. In response to the development instruction, a child application base library of the second parent application is obtained via the child application developer tool. A child application running environment of the second parent application is created by loading the child application base library. Further, development processing for the child application of the second parent application is performed in the child application running environment.Type: GrantFiled: May 13, 2021Date of Patent: August 15, 2023Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Wenliang Dai, Canhui Huang
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Publication number: 20230105835Abstract: A preparation method of CsDFP for aqueous negative electrode slurry includes carrying out ion exchange reactions with LiPO2F2 and a cesium source. The activation energy of Li+ intercalation in the negative electrode is reduced due to the existence of Cs+, leading to a better rate performance. Further, the impedance growth rate of the batteries is reduced and the high temperature storage performance is excellent since PO2F2— participates in the electrochemical reaction to form a stable low-impedance SEI film on the surface of the negative electrode plate. Moreover, films are continuously formed to repair the SEI films under the gradual release of CsDFP, which is conducive to inhibiting the growth of lithium dendrites during long-term high-rate cycling, thereby obtaining an improved cycle performance.Type: ApplicationFiled: September 21, 2022Publication date: April 6, 2023Inventors: CHONG MAO, Jing Bai, Pipi Wang, Dongyou Pan, Yi An Zeng, Wenliang Dai, Xiaobing Dai
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Publication number: 20210271456Abstract: This disclosure includes a child application development method. In the method, an interface of a child application developer tool is displayed. The child application developer tool is a native child application developer tool of a first parent application that is configured with an extension corresponding to development processing for a child application of a second parent application. A development instruction for the child application of the second parent application is received via the interface. In response to the development instruction, a child application base library of the second parent application is obtained via the child application developer tool. A child application running environment of the second parent application is created by loading the child application base library. Further, development processing for the child application of the second parent application is performed in the child application running environment.Type: ApplicationFiled: May 13, 2021Publication date: September 2, 2021Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Wenliang DAI, Canhui HUANG
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Patent number: 8949102Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure.Type: GrantFiled: February 24, 2012Date of Patent: February 3, 2015Assignee: Cadence Design Systems, Inc.Inventors: Wenliang Dai, Lanbing Chen, Guoying Feng, Ping Liu, Dennis Nagle, Jilin Tan, Wenjian Zhang, Qi Zhao, ZhongYong Zhou
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Patent number: 8631381Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) associated with an electronic circuit design. Embodiments may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the circuit design and generating a three dimensional adaptive mesh model that is based upon, at least in part, the extracted EM model. Numerous other features are also within the scope of the present disclosure.Type: GrantFiled: February 24, 2012Date of Patent: January 14, 2014Assignee: Cadence Design Systems, Inc.Inventors: Wenliang Dai, Lanbing Chen, Guoying Feng, Ping Liu, Dennis Nagle, Jilin Tan, Wenjian Zhang, Qi Zhao, ZhongYong Zhou
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Patent number: 8539422Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure.Type: GrantFiled: February 24, 2012Date of Patent: September 17, 2013Assignee: Cadence Design Systems, Inc.Inventors: Wenliang Dai, Lanbing Chen, Guoying Feng, Ping Liu, Dennis Nagle, Jilin Tan, Wenjian Zhang, Qi Zhao, ZhongYong Zhou
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Patent number: 8448117Abstract: An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size.Type: GrantFiled: November 2, 2009Date of Patent: May 21, 2013Assignee: Cadence Design Systems, Inc.Inventors: Wenliang Dai, Zhongyong Zhou, Zhangmin Zhong
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Publication number: 20120221988Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) associated with an electronic circuit design. Embodiments may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the circuit design and generating a three dimensional adaptive mesh model that is based upon, at least in part, the extracted EM model. Numerous other features are also within the scope of the present disclosure.Type: ApplicationFiled: February 24, 2012Publication date: August 30, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Wenliang DAI, Lanbing CHEN, Guoying FENG, Ping LIU, Dennis NAGLE, Jilin TAN, Wenjian ZHANG, Qi ZHAO, ZhongYong ZHOU
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Publication number: 20120221312Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure.Type: ApplicationFiled: February 24, 2012Publication date: August 30, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Wenliang DAI, Lanbing CHEN, Guoying FENG, Ping LIU, Dennis NAGLE, Jilin TAN, Wenjian ZHANG, Qi ZHAO, ZhongYong ZHOU
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Publication number: 20120221990Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure.Type: ApplicationFiled: February 24, 2012Publication date: August 30, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Wenliang DAI, Lanbing CHEN, Guoying FENG, Ping LIU, Dennis NAGLE, Jilin TAN, Wenjian ZHANG, Qi ZHAO, ZhongYong ZHOU
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Publication number: 20100205572Abstract: An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size.Type: ApplicationFiled: November 2, 2009Publication date: August 12, 2010Applicant: Cadence Design Systems, Inc.Inventors: Wenliang Dai, Zhongyong Zhou, Zhangmin Zhong