Patents by Inventor Wen-Lin Chen
Wen-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125849Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.Type: ApplicationFiled: March 8, 2023Publication date: April 18, 2024Inventors: Jung-Yin CHIEN, Po-Yen TSENG, Pin-Lin HUANG, Wen-Chih CHEN
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Publication number: 20240121935Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Y.L. Cheng, Tzu-Wen Pan, Yu-Hsien Lin, Ryan Chia-Jen Chen
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240113112Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
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Patent number: 11935795Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20230378021Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: July 26, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 11784106Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: July 29, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 11508640Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: May 14, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20220367315Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20220050347Abstract: A method for fast and convenient manufacture of liquid crystal display panels of different sizes without retooling provides an array substrate having a first display area of a first size. A closed-shaped sealant is coated onto the array substrate, the sealant defining a second display area of a second size, the second display area including an actual display area and an undesired display area adjacent to the actual display area and the sealant. Liquid crystals are applied in the second display area and sealing and coupling are carried out to obtain a liquid crystal cell, the liquid crystal cell being cut along an outer periphery of the sealant to obtain a working liquid crystal display panel of the desired size.Type: ApplicationFiled: July 8, 2021Publication date: February 17, 2022Inventors: ZHENG-XIA HE, NING FANG, YUAN XIONG, HUI WANG, WEN-LIN CHEN, CHIH-CHUNG LIU
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Publication number: 20220036780Abstract: An electrical conductivity test structure for testing an electrical conductivity of target traces in a display panel includes a controller, a first conductive layer, and a second conductive layer. The first conductive layer includes first and second traces. The at least one first trace and the at least one second trace are connected in parallel. Each first trace connects with the target trace and with the controller and each second trace connects with the target trace and with the controller. The second conductive layer connects with the first trace but is electrically insulated from the second trace. The second conductive layer transmits test signals to the first trace to test electrical conductivity between the controller and the target trace.Type: ApplicationFiled: March 19, 2021Publication date: February 3, 2022Inventors: QI XU, RUI LI, YUAN XIONG, HUI WANG, WEN-LIN CHEN, CHIH-CHUNG LIU
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Patent number: 11017738Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.Type: GrantFiled: November 27, 2018Date of Patent: May 25, 2021Assignee: Century Technology (Shenzhen) Corporation LimitedInventors: Qi Xu, Ming-Tsung Wang, Wen-Lin Chen, Jing Zhu
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Publication number: 20200279790Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 14, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 10658263Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: May 31, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20200013362Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.Type: ApplicationFiled: November 27, 2018Publication date: January 9, 2020Inventors: QI XU, MING-TSUNG WANG, WEN-LIN CHEN, JING ZHU
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Publication number: 20190371699Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 8779892Abstract: A wireless illumination controller with the function to set the lowest driving power includes a microprocessor, a driver, an illumination control switch, and a wireless receiving module. The microprocessor is built in with an adjustable lowest power and connected with the driver, the illumination control switch, the wireless receiving module and a power processing module. The illumination control switch is used to set the lowest power of the microprocessor. After the wireless receiving module receives a wireless illumination adjustment command, the power of the driving signal output from the driver is controlled to be not lower than the lowest power. Therefore, when a user adjusts the illumination, the driving power is never lower than the lowest driving power of the corresponding light bulb, thereby avoiding flickering.Type: GrantFiled: December 29, 2011Date of Patent: July 15, 2014Assignee: Arc Technology Co., Ltd.Inventor: Wen-Lin Chen
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Publication number: 20140003019Abstract: A remotely controllable outlet assembly has a case, an outlet panel and a power remote control device. The outlet panel is mounted on the case. The power remote control device has a remote controller and a main control apparatus. The main control apparatus is mounted in the case and is electrically connected to a neutral wire, a live wire and an outlet of the outlet panel. The main control apparatus electrically connects or disconnects the neutral wire and the live wire to or from the outlet according to an operation command emitted from the remote controller. Therefore, the outlet is remotely controllable. The main control apparatus is embedded in the wall, so that the outlet assembly does not spoil the interior decoration of the house.Type: ApplicationFiled: September 11, 2012Publication date: January 2, 2014Inventors: Wen-Lin CHEN, Chi-Kan LIN, Chung-Chi CHIANG