Patents by Inventor Wen Ling Huang
Wen Ling Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009033Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: GrantFiled: June 20, 2023Date of Patent: June 11, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
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Patent number: 12000957Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals and ranges determined from the radar signals. In particular, the disclosure provides an intrusion detection system receiving ranges and velocities for targets detected based on radar signals, determining a potential ghost target from the received velocities and confirming the potential ghost target based on estimated ranges and perturbations of the vehicle speed.Type: GrantFiled: June 24, 2021Date of Patent: June 4, 2024Assignee: INTEL CORPORATIONInventors: Vuk Lesi, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Manoj Sastry, Ivan Simoes Gaspar, Qian Wang
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Patent number: 11983090Abstract: A method of analyzing source code includes receiving, by a processor, an updated version of a computer program, the updated version including a source code. The method also includes preprocessing, by a compiler, the source code for a target computing platform. Preprocessing the source code by the compiler includes identifying a macro condition associated with one or more computer instructions enclosed by a macro, determining object code corresponding to the one or more computer instructions based on a current value of the macro condition, and generating object code and macro information for output to a debugger, the macro information including one or more breakpoint conditions in the macro.Type: GrantFiled: February 17, 2022Date of Patent: May 14, 2024Assignee: International Business Machines CorporationInventors: Xiao Ling Chen, Wen Ji Huang, Heng Wang, Sheng Shuang Li, Wen Bin Han, Peng Hui Jiang
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Patent number: 11972984Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: December 26, 2022Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Publication number: 20240136291Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.Type: ApplicationFiled: January 12, 2023Publication date: April 25, 2024Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11966322Abstract: A method, computer program product and system are provided for preloading debug information based on the presence of incremental source code files. Based on parsed input parameters to a source code debugger, a source code repository and a local storage area are searched for an incremental file. In response to the incremental file being located, a preload indicator in the incremental file, which is a source code file, is set. Based on the preload indicator being set, debug symbol data from the incremental file is merged to a preload symbol list. In response to receiving a command to examine the debug symbol data from the incremental file, the preload symbol list is searched for the requested debug symbol data.Type: GrantFiled: November 25, 2020Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Xiao Ling Chen, Xiao Xuan Fu, Jiang Yi Liu, Zhan Peng Huo, Wen Ji Huang, Qing Yu Pei, Min Cheng, Yan Huang
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Patent number: 11947966Abstract: A computer-implemented method includes preprocessing, by a compiler, a plurality of macros in a computer program. Preprocessing a macro includes identifying a compile time condition associated with the macro. Preprocessing the macro further includes determining a current value of the compile time condition at the time of compiling a computer instruction and a previous value of the compile time condition. Preprocessing the macro further includes determining a set of computer instructions enclosed by the macro. The method further includes storing a macro information record that includes the compile time condition, the current value and the previous value of the compile time condition, and an identification of the set of computer instructions enclosed by the macro.Type: GrantFiled: October 11, 2021Date of Patent: April 2, 2024Assignee: International Business Machines CorporationInventors: Wen Ji Huang, Xiao Ling Chen, Wen Bin Han, Sheng Shuang Li, Xiao Zhen Zhu
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Publication number: 20240088246Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
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Publication number: 20210325508Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals is provided. In particular, the disclosure provides an intrusion detection system adapted to receive radar signals and distinguish a potential ghost target from a legitimate target based on a signal to noise ratio of the radar signals and a range to the ghost target and the legitimate target.Type: ApplicationFiled: June 24, 2021Publication date: October 21, 2021Applicant: Intel CorporationInventors: Qian Wang, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Vuk Lesi, Manoj Sastry, Ivan Simoes Gaspar
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Publication number: 20210318414Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals and ranges determined from the radar signals. In particular, the disclosure provides an intrusion detection system receiving ranges and velocities for targets detected based on radar signals, determining a potential ghost target from the received velocities and confirming the potential ghost target based on estimated ranges and perturbations of the vehicle speed.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Vuk Lesi, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Manoj Sastry, Ivan Simoes Gaspar, Qian Wang
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Patent number: 10631170Abstract: Certain embodiments herein are directed to managing wireless spectrum, which may include recommending or transmitting spectrum usage changes to one or more wireless devices. A spectrum management system comprising one or more computers may receive spectrum usage information associated with one or more wireless devices. The spectrum management system may generate a spectrum usage map based on the received information. Based on the spectrum usage map, a spectrum usage change is determined and transmitted to one or more wireless devices. The wireless devices may change their operation in accordance with the spectrum usage change.Type: GrantFiled: September 24, 2013Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Srikathyayani Srikanteswara, Carlos Cordeiro, Kerstin Johnsson, Anthony Lamarca, Jaideep Moses, Wen-Ling Huang, Christian Maciocco, Shilpa Talwar, Meiyuan Zhao, Jeffrey Foerster, Xue Yang
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Patent number: 9627765Abstract: Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform.Type: GrantFiled: July 23, 2013Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Helen Kankan Pan, Wen-Ling Huang, Harry G. Skinner
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Publication number: 20150087323Abstract: Certain embodiments herein are directed to managing wireless spectrum, which may include recommending or transmitting spectrum usage changes to one or more wireless devices. A spectrum management system comprising one or more computers may receive spectrum usage information associated with one or more wireless devices. The spectrum management system may generate a spectrum usage map based on the received information. Based on the spectrum usage map, a spectrum usage change is determined and transmitted to one or more wireless devices. The wireless devices may change their operation in accordance with the spectrum usage change.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Inventors: Srikathyayani Srikanteswara, Carlos Cordeiro, Kerstin Johnsson, Anthony Lamarca, Jaideep Moses, Wen-Ling Huang, Christian Maciocco, Shilpa Talwar, Meiyuan Zhao, Jeffrey Foerster, Xue Yang
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Publication number: 20150029064Abstract: Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform.Type: ApplicationFiled: July 23, 2013Publication date: January 29, 2015Inventors: Helen Kankan Pan, Wen-Ling Huang, Harry G. Skinner
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Publication number: 20110031588Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Pamela J. Welch, Wen Ling Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi