Patents by Inventor Wenlong Cai

Wenlong Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970523
    Abstract: The present invention discloses a polypeptide and application thereof. By modifying oxyntomodulin (OXM), hybridizing OXM with a peptide sequence of Exenatide, including enabling the polypeptide to be resistant to DPP-4 enzyme degradation through amino acid modification, and conjugating fatty acid chains at the same time, an OXM hybrid peptide having longer pharmacologic action time and better weight losing effects is obtained. Synthesis of a target polypeptide is fast realized by an orthogonal protection strategy solid-phase synthesis method, and a crude product is purified and freeze-dried to obtain the OXM hybrid peptide.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: April 30, 2024
    Assignee: CHINA PHARMACEUTICAL UNIVERSITY
    Inventors: Hai Qian, Wenlong Huang, Xingguang Cai, Chengye Li, Chunxia Liu, Yuxuan Dai
  • Publication number: 20240056065
    Abstract: Disclosed are an ultrafast electric pulse generation and detection device and a use method thereof. The device includes a laser and an electric pulse generator. The electric pulse generator includes: a photoelectric material layer including an optically controlled switching region for responding to excitation light generated by the laser; an insulating layer formed on the photoelectric material layer, wherein a switch structure exists at a position of the insulating layer corresponding to the optically controlled switching region, so that the optically controlled switching region is partially exposed or completely exposed; transmission lines are formed on the insulating layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 15, 2024
    Applicant: BEIHANG UNIVERSITY
    Inventors: Boyu ZHANG, Wenlong CAI, Chen XIAO, Xiangyu ZHENG, Jiaqi WEI, Weisheng ZHAO
  • Publication number: 20240045160
    Abstract: Disclosed are a low-loss coplanar waveguide bonding structure and a manufacturing method thereof, relating to the technical field of semiconductor. The low-loss coplanar waveguide bonding structure includes: a first coplanar waveguide on a first substrate, a second coplanar waveguide on a second substrate and having a same structure as the first coplanar waveguide, and a plurality of two-dimensional heterostructures connecting conductors of the first coplanar waveguide and the second coplanar waveguide in a one-to-one correspondence, where the two-dimensional heterostructures includes: a two-dimensional conductive material layer for signal transmission and a two-dimensional dielectric material layer under the two-dimensional conductive material layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 8, 2024
    Applicant: BEIHANG UNIVERSITY
    Inventors: Chen XIAO, Rui XU, Boyu ZHANG, Xiangyu ZHENG, Wenlong CAI, Jiaqi WEI, Weisheng ZHAO
  • Patent number: 11170833
    Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 9, 2021
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Kaihua Cao, Erya Deng, Wenlong Cai, Shaohua Yan
  • Publication number: 20200342927
    Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Weisheng Zhao, Kaihua Cao, Erya Deng, Wenlong Cai, Shaohua Yan
  • Patent number: 10388344
    Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 20, 2019
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Wenlong Cai
  • Publication number: 20180277184
    Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Wenlong Cai