Abstract: The disclosure discloses a data rearrangement method. The method includes: determining N/4 4-4 data rearrangement networks in a current N-N rearrangeable non-blocking Benes network; determining sequence numbers of input data of each 4-4 data rearrangement network according to a preset data rearrangement rule; and determining, according to sequence numbers corresponding to input data of switch circuits in the 4-4 data rearrangement networks, a data output mode of the switch circuits, and outputting the input data of the current 4-4 data rearrangement network according to the data output mode corresponding to each switch circuit in the current 4-4 data rearrangement network, N=2n, and n being a positive integer greater than 1. The disclosure also discloses a data rearrangement apparatus and a storage medium.

Abstract: A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.

Abstract: A data transmission method and system, related to the field of communication, resolve the problem of data transmission in a software defined radio (SDR) system. The method includes: a data path mapping data received from an RFC to a preset unified time reference, then collecting data and caching the data obtained from collection; after the data path caches the data obtained from the collection, an event table generating a downlink data processing event, and scheduling a vector processor to perform downlink data processing. The technical solution provided in the embodiments of the present document is applied to the SDR and achieves the data transmission at high utilization rate.

Abstract: Provided are a method and vector computing unit for implementing de-scrambling and de-spreading, and a computer storage medium. The method includes that: an operation of complex multiplication on baseband data and corresponding de-scrambling and de-spreading codes is performed by adopting data transformation and addition, and data obtained by the complex multiplication is stored into a vector register file; a row of data obtained by the complex multiplication is read from the vector register file, every two adjacent pieces of data in the row of data are accumulated to obtain a half row of data, a ¼ row of data, and finally one piece of accumulated data; and the accumulation processing is continued on other rows of data to implement accumulation of each row of data obtained by the complex multiplication in the vector register file.

Abstract: Disclosed a device scheduling method. A Task Description (TD) in a task queue is read and parsed, to acquire task information of a task corresponding to the TD; and when it is determined that the task has met a starting condition and the task is a task with a highest priority among tasks which currently meet the starting condition, a preset parameter is acquired according to the task information, and the parameter is configured to a device intended to complete the task. A task manager and a storage medium is also disclosed.

Abstract: Provided are a method and vector computing unit for implementing de-scrambling and de-spreading, and a computer storage medium. The method includes that: an operation of complex multiplication on baseband data and corresponding de-scrambling and de-spreading codes is performed by adopting data transformation and addition, and data obtained by the complex multiplication is stored into a vector register file; a row of data obtained by the complex multiplication is read from the vector register file, every two adjacent pieces of data in the row of data are accumulated to obtain a half row of data, a ¼ row of data, and finally one piece of accumulated data; and the accumulation processing is continued on other rows of data to implement accumulation of each row of data obtained by the complex multiplication in the vector register file.

Abstract: A data transmission method and system, related to the field of communication, resolve the problem of data transmission in a software defined radio (SDR) system. The method includes: a data path mapping data received from an RFC to a preset unified time reference, then collecting data and caching the data obtained from collection; after the data path caches the data obtained from the collection, an event table generating a downlink data processing event, and scheduling a vector processor to perform downlink data processing. The technical solution provided in the embodiments of the present document is applied to the SDR and achieves the data transmission at high utilization rate.

Abstract: A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.

Abstract: The disclosure discloses a method of supporting arbitrary replacement of multiple data units, which includes: configuring patterns for arbitrary position replacement of N data units; and during a process of data unit replacement, performing a replacement operation on the N data units according to the configured patterns. The disclosure further discloses a device of supporting arbitrary replacement of multiple data units. By means of the method and device, an occupied area of a data unit replacement circuit in a chip can be decreased, and power consumption can be reduced.

Abstract: The disclosure discloses a method of supporting arbitrary replacement of multiple data units, which includes: configuring patterns for arbitrary position replacement of N data units; and during a process of data unit replacement, performing a replacement operation on the N data units according to the configured patterns. The disclosure further discloses a device of supporting arbitrary replacement of multiple data units. By means of the method and device, an occupied area of a data unit replacement circuit in a chip can be decreased, and power consumption can be reduced.