Patents by Inventor Wensen Hung

Wensen Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260130267
    Abstract: A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.
    Type: Application
    Filed: January 5, 2026
    Publication date: May 7, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
  • Patent number: 12622274
    Abstract: A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 5, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20260107828
    Abstract: A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.
    Type: Application
    Filed: December 15, 2025
    Publication date: April 16, 2026
    Inventors: Wensen Hung, Tsung-Yu Chen, Hsuan-Ning Shih, Wen-Hsin Wei
  • Publication number: 20260082941
    Abstract: A semiconductor package includes a substrate, a die, a first bonding material, a second bonding material and a heat dissipation system. The die is connected to the substrate. The first bonding material is disposed on the substrate beside the die. The second bonding material is disposed on and covers the die. The heat dissipation system, having a bottom surface in contact with the second bonding material, is disposed on the second bonding material over the die and on the first bonding material on the substrate. The heat dissipation system is fixed to the substrate through the first bonding material. The bottom surface of the heat dissipation system is fixed to the die through the second bonding material with a bonding interface existing therebetween, and the bonding interface includes a first curved surface.
    Type: Application
    Filed: September 19, 2024
    Publication date: March 19, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yu Chen, Wensen Hung, Jung-Wei Cheng
  • Publication number: 20260068745
    Abstract: A package structure includes a package substrate, a package module on the package substrate, an outer molding material layer on the package substrate around the package module, a thermal interface material (TIM) layer on the package module, and a package lid on the TIM layer and attached to the outer molding material layer. The package lid includes a bottom lid portion having a first coefficient of thermal expansion (CTE), and a top lid portion attached to the bottom lid portion and having a second CTE less than the first CTE.
    Type: Application
    Filed: September 4, 2024
    Publication date: March 5, 2026
    Inventors: Wensen Hung, Yen-Fu Su, Tsung-Yu Chen
  • Publication number: 20260068671
    Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is bonded over the substrate. The lid structure is bonded over the substrate and thermally coupled to the package structure, wherein the lid structure includes a fluid chamber and a plurality of spring members disposed in the fluid chamber, wherein each of the plurality of spring members is connected between an upper plate and a lower plate of the fluid chamber.
    Type: Application
    Filed: August 27, 2024
    Publication date: March 5, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Patent number: 12550775
    Abstract: A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.
    Type: Grant
    Filed: July 30, 2024
    Date of Patent: February 10, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
  • Patent number: 12550729
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 10, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 12538835
    Abstract: A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 27, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wensen Hung, Tsung-Yu Chen, Hsuan-Ning Shih, Wen-Hsin Wei
  • Publication number: 20260005100
    Abstract: A semiconductor package includes one or more semiconductor dies, and a lid disposed on the one or more semiconductor dies. One or more thermoelectric coolers are disposed on or in the lid. Each thermoelectric cooler is positioned at a predetermined hotspot of the one or more semiconductor dies. In one method of operating such a semiconductor package, functions are run on one or more semiconductor dies of the semiconductor package. During the running of these functions, one or more predetermined hotspots of the one or more semiconductor dies are cooled by operating a thermoelectric cooler positioned at each respective predetermined hotspot.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Inventors: Sheng-Han Tsai, Wensen Hung, Wei-Kong Sheng, Tsung-Yu Chen, Yen-Pu Chen
  • Publication number: 20250372534
    Abstract: A semiconductor package includes a substrate, a semiconductor device disposed over the substrate, a ring structure bonded to the substrate, and a lid structure. The ring structure includes a main portion surrounding the semiconductor device and a cantilever portion extended toward the semiconductor device and bonded to a top surface of the semiconductor device. The lid structure is bonded to the ring structure and includes a contact portion bonded to the top surface of the semiconductor device.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 4, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Min Chang, Chien-Chang Lin, Wensen Hung, Hsuan-Cheng Kuo, Shih-Hui Wang, Tzu-Shiun Sheu
  • Publication number: 20250372572
    Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die. The first die may include a first semiconductor substrate, a first bonding layer over the first semiconductor substrate, and a first die connector in the first bonding layer. The first bonding layer may include a first portion including a first material and a second portion including a second material, wherein the first material is different from the second material. A surface of the first bonding layer may include a surface of the first portion, a surface of the second portion, and a surface of the first die connector.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 4, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Wensen Hung, Yen-Pu Chen
  • Publication number: 20250372480
    Abstract: A package structure according to the present disclosure includes a package substrate, a package component disposed over the package substrate, a lid disposed over the package substrate and the package component, and an active cooling device embedded in the lid.
    Type: Application
    Filed: July 25, 2025
    Publication date: December 4, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Wensen Hung, Yen-Pu Chen
  • Publication number: 20250364362
    Abstract: An exemplary heat-dissipating lid includes a thermally conductive casing having an upper plate and a lower plate, a first wick structure disposed on the lower plate and spanning an opening of the lower plate, and a hollow interior region disposed within the thermally conductive casing between the upper plate and the lower plate and between the upper plate and the first wick structure. The opening of the lower plate is configured to receive a second wick structure that is disposed on an integrated circuit (IC) die. In some embodiments, the heat-dissipating lid further includes thermally conductive columns disposed in the hollow interior region and between the upper plate and the lower plate. In some embodiments, the opening is a first opening, the thermally conductive casing further has mounting flanges extending from the lower plate, and the mounting flanges define a second opening for receiving the IC die.
    Type: Application
    Filed: July 31, 2025
    Publication date: November 27, 2025
    Inventors: Wei-Kong SHENG, Hsin Ting LIN, Wensen HUNG
  • Publication number: 20250364458
    Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die, which may include a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a first seal ring. The first interconnect structure may include a first plurality of dielectric layers, a first plurality of metallization patterns in the first plurality of dielectric layers. The first seal ring may be in the first plurality of dielectric layers and may encircle the first plurality of metallization patterns in a top-down view. The integrated circuit package may further include a first bonding layer on the first interconnect structure, a first die connector and a second die connector in the first bonding layer. The first seal ring may encircle the first die connector and the second die connector may be outside the first seal ring in the top-down view.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 27, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Wensen Hung, Yen-Pu Chen
  • Publication number: 20250357258
    Abstract: An electronic apparatus, a semiconductor package module and a method for manufacturing the semiconductor package module are provided. The semiconductor package module includes: an encapsulated structure, including a device die and an encapsulant laterally enclosing the device die; a package substrate, attached to a first side of the encapsulated structure; a composite thermal interfacial structure, disposed on a second side of the encapsulated structure, and including thermally conductive elements arranged side by side or stacked along a vertical direction; a ring structure, attached to the package substrate and laterally surrounding the encapsulated structure; and a heat spreader, attached to the second side of the encapsulated structure through the composite thermal interfacial structure, and supported by the ring structure.
    Type: Application
    Filed: July 30, 2025
    Publication date: November 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen, Jia-Syuan Li, Chen-Hsiang Lao, Hung-Chi Li
  • Publication number: 20250357262
    Abstract: A package assembly includes a device package, a ring structure, and a lid on the ring structure. The device package includes a package substrate, a first die coupled to the package substrate, and a second die aside the first die and coupled to the package substrate. The ring structure is on the package substrate and surrounds the first and second dies. The lid is thermally coupled to the first die and includes a vapor chamber, a working fluid in the vapor chamber, a wicking structure in the vapor chamber, first and second pillars distributed in the vapor chamber. The first pillars are coated with a first powder layer. The second pillars are directly over the first die, and the first and second pillars are arranged in a staggered manner.
    Type: Application
    Filed: May 16, 2024
    Publication date: November 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Wei-Kong Sheng, Tsung-Yu Chen, Cheng-Hung Lin, Meng-Tsan Lee
  • Publication number: 20250357447
    Abstract: In an embodiment, a method includes attaching a die to an interposer; attaching and electrically coupling the interposer to a package substrate; attaching a package lid and a first thermal interface material to the die and to the package substrate; attaching and electrically coupling the package substrate to an assembly substrate; and attaching a heat sink and a second thermal interface material to the package lid using a screw extending between the heat sink and the assembly substrate, the heat sink comprising first sensing modules in physical contact with the second thermal interface material.
    Type: Application
    Filed: July 29, 2025
    Publication date: November 20, 2025
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20250349769
    Abstract: A semiconductor package according to the present disclosure includes an interposer and a component mounted on the interposer. The component includes a first die and a second die disposed over the first die having a surface away from the first die. The second die includes a metal pad. A top surface of the metal pad is coplanar with the surface. The metal pad is electrically floating.
    Type: Application
    Filed: July 25, 2025
    Publication date: November 13, 2025
    Inventors: Sheng-Han Tsai, Tsung-Yu Chen, Wensen Hung, Yen-Pu Chen
  • Publication number: 20250348064
    Abstract: One or more sensors are integrated into a processor module that includes a semiconductor package and a heat sink. A plurality of processor modules is present in a server, and data from each processor module is sent to a digitally integrated monitoring system which can be part of a data center hardware monitoring system. The server may be one of many servers located in a data center. The data may be further sent to a remote data center maintenance center that concurrently monitors several data centers. When compared to different benchmarks, the data can be used to determine in real time whether maintenance is needed for a given processor module.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 13, 2025
    Inventors: WENSEN HUNG, TSUNG-YU CHEN