Patents by Inventor Wensen Hung

Wensen Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961779
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Publication number: 20240105530
    Abstract: In an embodiment, a device includes: an integrated circuit package including: a package component; and a package stiffener attached to the package component; and a heat spreader attached to the integrated circuit package, a main portion of the heat spreader disposed above the package stiffener, a protruding portion of the heat spreader extending through the package stiffener; an elastic adhesive material between the main portion of the heat spreader and the package stiffener; and a thermal interface material between the protruding portion of the heat spreader and the package component, the thermal interface material different from the elastic adhesive material.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20240088093
    Abstract: In an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Wensen Hung, Tsung-Yu Chen, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11929293
    Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Tsung-Yu Chen
  • Publication number: 20240038627
    Abstract: A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.
    Type: Application
    Filed: January 6, 2023
    Publication date: February 1, 2024
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20240038617
    Abstract: A package structure includes a substrate, a semiconductor package disposed over the substrate, a first lid structure disposed over the substrate, and a second lid structure disposed over the semiconductor package and the first lid structure. The first lid structure includes an opening exposing a region of the semiconductor package. A thermal interface material is disposed between the second lid structure and the semiconductor package, and a phase change adhesive is disposed between the second lid structure and the first lid structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Jia-Syuan Li, Tsung-Yu Chen
  • Publication number: 20240030084
    Abstract: A 3D semiconductor package provided herein includes a package substrate; a semiconductor package bonded to the package substrate; a heat dissipation unit attached to the semiconductor package, wherein the heat dissipation unit comprises a first heat dissipation component and a second heat dissipation component attached to the first heat dissipation component; and a first interface material disposed between the first heat dissipation component and the second heat dissipation component, wherein the first interface material is a phase change material.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20230386945
    Abstract: A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.
    Type: Application
    Filed: August 30, 2022
    Publication date: November 30, 2023
    Inventors: Wensen Hung, Tsung-Yu Chen, Hsuan-Ning Shih, Wen-Hsin Wei
  • Publication number: 20230369162
    Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11810833
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Publication number: 20230335449
    Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.
    Type: Application
    Filed: June 17, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
  • Publication number: 20230326826
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11721602
    Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
  • Patent number: 11715675
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Publication number: 20230144244
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: January 12, 2023
    Publication date: May 11, 2023
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20230075909
    Abstract: An electronic apparatus, a semiconductor package module and a method for manufacturing the semiconductor package module are provided. The semiconductor package module includes: an encapsulated structure, including a device die and an encapsulant laterally enclosing the device die; a package substrate, attached to a first side of the encapsulated structure; a composite thermal interfacial structure, disposed on a second side of the encapsulated structure, and including thermally conductive elements arranged side by side or stacked along a vertical direction; a ring structure, attached to the package substrate and laterally surrounding the encapsulated structure; and a heat spreader, attached to the second side of the encapsulated structure through the composite thermal interfacial structure, and supported by the ring structure.
    Type: Application
    Filed: April 14, 2022
    Publication date: March 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen, Jia-Syuan Li, Chen-Hsiang Lao, Hung-Chi Li
  • Publication number: 20230071542
    Abstract: A semiconductor device including a package, a lid and a thermal interface material is provided. The package includes a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies. The lid is disposed on the packaging substrate, the lid includes a cover portion and foot portion extending from the cover portion to the packaging substrate, wherein the cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion includes foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate. The cover portion of the lid is attached to the package through the thermal interface material.
    Type: Application
    Filed: March 22, 2022
    Publication date: March 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yih-Ting Shen, Jia-Syuan Li, Tsung-Yu Chen
  • Publication number: 20230071418
    Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.
    Type: Application
    Filed: March 18, 2022
    Publication date: March 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Patent number: 11594469
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Publication number: 20230059983
    Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Tsung-Yu Chen