Abstract: A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.

Abstract: A semiconductor device includes a drain, a substrate, an epitaxial layer, and a semiconductor layer. The semiconductor layer includes a source region located on a side the semiconductor layer away from the epitaxial layer. A trench extending to the epitaxial layer is disposed on a side of the source region is away from the epitaxial layer. A gate, an electrode plate, a first shield gate, and a second shield gate are disposed in the trench. The electrode plate is located between the first shield gate and the second shield gate. The trench is further filled with an oxidized layer structure. The first shield gate and the second shield gate are separately spaced from the electrode plate to form electrode plate capacitance. One of the source region, the drain, and the gate is electrically connected to the electrode plate a first electrode, and a second one of the source region, the drain, and the gate is electrically connected to the shield gate structure.

Abstract: The present disclosure discloses an automatic leveling control method for a four-leg support working platform, which comprises the steps: determining the mass center position of the working platform, determining the main bearing quadrant and distinguishing active legs from the driven leg; adjusting the driven leg to weak state, controlling all legs to synchronously actuate for leveling; calculating the limit compensating actuation length of the driven leg, and performing compensating actuation until accomplishing the leveling process. The method is advantageous in: high speed, high robustness, no repeated oscillation. The mass center always stays within the bearing zone of the active legs, thus completely eliminating capsizing risk of the working platform. The compensating actuation of the driven leg ensures there is no weak leg, and hence high attitude and load-bearing stability of the working platform is achieved.

Abstract: A system configured for electro-thermal defrosting, desnowing and/or deicing includes (a) a component susceptible to accumulation of ice, frost, and/or snow, and (b) an electro-thermal multilayer on the component. The electro-thermal multilayer comprises a heating layer on an insulating layer, where the heating layer is configured for electrical connection to a source of pulsed power. The electro-thermal multilayer optionally includes a superhydrophobic layer. The component may be a photovoltaic panel, a wind turbine blade, a heat exchanger coil or fin, or an aircraft wing, e.g., of an electrified aircraft. The electro-thermal multilayer may be adhered to the component as a coating or removably secured to the component as a module.

Abstract: A landslide risk monitoring and early warning method based on real 3D includes the following steps: S1, multi-source data fusion processing: collecting landslide-related data for an integrated fusion processing; S2, large-scale scene modeling, and analysis; S3, mesoscale scene modeling and analysis; S4, small-scale scene modeling and analysis; S5, landslide knowledge association and entity database construction; S6, landslide risk multi-scale dynamic assessment; S7, landslide multi-indicator monitoring and early warning. A landslide hazard monitoring and early warning system based on real 3D is also disclosed. The above-mentioned landslide risk monitoring and early warning method and system based on real 3D can realize different scale data acquisition and real 3D modeling of landslide geological disasters, establishment of full-factor real 3D landslide scene database, multi-scale spatial-temporal dynamic monitoring and analysis of landslide risk, and timely and intelligent multi-indicator early warning.

Abstract: A method, a device, computer equipment and a storage medium for identify an illegal commodity. The method comprises: firstly, constructing a multi-modal knowledge graph according to a multi-modal knowledge graph data set, and extracting visual features of all visual modality entities and text features of all text modality entities in the knowledge graph; then obtaining a commodity image and a commodity text according to a database; then, generating commodity visual feature according to the commodity image; then generating the commodity text feature according to the commodity text; secondly, according to the visual features and text features, as well as the commodity visual feature and the commodity text feature, linking the commodity image and the commodity text to the knowledge graph by using an entity linking method; finally, obtaining the correlation between the commodity image and the commodity text according to the linked knowledge graph to determine the illegality of the commodity.

Abstract: Embodiments of this application provide a speaker module and a portable electronic device. The speaker module includes a first speaker module and a second speaker module. The first speaker module includes a first housing and a first speaker monomer accommodated in the first housing, and the first speaker monomer has a first diaphragm. The second speaker module includes a second housing and a second speaker monomer accommodated in the second housing, and the second speaker monomer has a second diaphragm. The first speaker module and the second speaker module are sequentially disposed in a vertical direction, and a vibration direction of the first diaphragm is opposite to a vibration direction of the second diaphragm, so that momentum variations (mv) ? of the speaker module are offset against each other, thereby resolving a problem that a vibration feeling is strong when the speaker module works.

Abstract: The present disclosure discloses a leveling control method for a multi-point support platform, which comprises the steps: respectively measuring and obtaining a load-bearing interaction matrix and a deformation interaction matrix of the platform to construct a load-bearing and deformation joint control matrix; calculating the optimal loads of the legs and measuring the current loads of the legs to obtain the load deviation rates of the legs, and determining if the platform warrants leveling in combination with the two-dimensional inclination angles of the platform; constructing a platform geometry and leg load joint control equation according to the two-dimensional inclination angles of the platform, the load deviations of the legs and the load-bearing and deformation joint control matrix, calculating the actuation quantities of the legs and performing synchronous leveling; and determining the load deviation rates of the legs and the two-dimensional inclination angles of the platform cyclically and performing

Abstract: A chip package module, including a first conductive frame, a first bare die disposed on the first conductive frame, and a second conductive frame disposed at an interval beside the first conductive frame. The chip package module further includes a first conductive connecting sheet, a second bare die, and a conductive cover plate. The first conductive connecting sheet is connected to a surface of the first bare die away from the first conductive frame, and extends to be lapped on the second conductive frame. The second bare die is laminated on the first bare die and is connected to the first conductive connecting sheet. The conductive cover plate is connected to a surface of the second bare die away from the first conductive frame and extends to be connected to the first conductive frame.

Abstract: Embodiments of the present invention provide a power semiconductor device, a related circuit, a chip, an electronic device, and a preparation method. The semiconductor device includes a first-conductivity-type first semiconductor layer, an insulated gate bipolar transistor (IGBT) comprising an IGBT region, and a diode comprising a diode region. The semiconductor device also includes a second-conductivity-type second semiconductor layer disposed on a first surface of the first semiconductor layer. A first-conductivity-type emitter region is disposed on a surface, of the second semiconductor layer located in the IGBT region, that faces away from the first semiconductor layer, and a collector layer and an electrode layer that are disposed under the second surface of the first semiconductor layer.

Abstract: An IGBT has a front-surface device region, an IGBT drift region, an IGBT buffer region, and an IGBT collector region that are sequentially connected. The front-surface device region may include a cell region, a field plate region, and a field limiting ring region. The IGBT drift region has a first-type doping element, the IGBT buffer region has a first-type doping element, and a concentration of the first-type doping element in the IGBT buffer region is greater than a concentration of the first-type doping element in the IGBT drift region. The IGBT collector region includes a cell collector region, a field plate collector region, and a field limiting ring collector region. The IGBT collector region has a second-type doping element, and a concentration of a second-type doping element in the cell collector region is greater than a concentration of a second-type doping element in the field plate collector region.

Abstract: An example SiC MOSFET includes a SiC semiconductor substrate (SSS), a drift layer on the SSS having a fin-shaped channel layer (FSCL) with a source region and a first insulated isolating layer. The FSCL does not cover the first insulated isolating layer, and the FSCL and the source region are of a stacking structure, and includes a gate electrode on the first insulated isolating layer that is separately on two sides of the stacking structure, a gate oxide layer between the gate electrode and the stacking structure, a second insulated isolating layer that covers an external side wall and an upper surface of the gate electrode, and a source electrode that covers the first insulated isolating layer, the second insulated isolating layer, and the source region. The SiC MOSFET further includes a drain electrode on a side of the SSS that is separated from the drift layer.

Abstract: Provided is a logistics palletizing system.

Abstract: A semiconductor device includes a drift region, a first electrode structure, and a second electrode structure, and the first electrode structure and the second electrode structure are located on a same side of the drift region. The first electrode structure includes a first insulation layer and a first electrode. The first insulation layer is located on a periphery of the first electrode. The second electrode structure includes a second insulation layer and a second electrode. The second insulation layer is located on a periphery of the second electrode. A buffer structure is disposed between the first electrode and the second electrode, and the buffer structure is configured to increase accumulation of carriers in the drift region when the semiconductor device is turned on. The buffer structure is disposed between the first electrode and the second electrode, so that flow of carriers stored in the drift region is buffered.

Abstract: A diode and a power circuit are provided. The diode may include: a first electrode layer; a drift layer located above the first electrode layer, a doping concentration of the drift layer is less than that of the first electrode layer; and the drift layer includes an active region and a terminal region surrounding the active region; a second electrode layer disposed in the active region, where the second electrode layer and the drift layer are doped with impurities of different properties; and the second electrode layer includes a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, where the first region is connected to a power supply through a first conductor, and the second region is connected to the power supply through a second conductor, a first resistor, and the first conductor sequentially.

Abstract: The present disclosure provides a method for estimating a body size and weight of a pig based on deep learning, and relates to the technical field of deep learning. The present disclosure predicts the weight of the pig by using a convolutional neural network. Relevant features are learned by the convolutional neural network, and feature engineering extraction is not needed to be established, so that extracted features are more comprehensive, and the convolutional neural network is superior to a linear model in processing of noisy data and nonlinear problems of data. Images of the pig are shot by an ordinary two-dimensional (2d) color camera.

Abstract: A terminal structure of a power device includes a substrate and a plurality of field limiting rings disposed on a first surface of the substrate. The substrate includes a drift layer and a doped layer. The doped layer is formed through diffusion inward from the first surface of the substrate. The doped layer and the drift layer are a first conductivity type, and an impurity concentration of the doped layer is greater than an impurity concentration of the drift layer. The field limiting rings are a second conductivity type. In the terminal structure, lateral diffusion of impurities in the field limiting rings is limited through a design of the doped layer.

Abstract: A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.

Abstract: The technology of this disclosure relates to an IGBT chip integrating a temperature sensor, and relates to the field of power device technologies, to improve accuracy of temperature monitoring of the IGBT chip. The IGBT chip integrating the temperature sensor includes a cell region, an emitter pad, a gate pad, a gate finger structure, a temperature sensing module, and a conductive shielding structure. The emitter pad is electrically connected to emitters of a plurality of IGBT cells. The gate finger structure is connected between the gate pad and gates of the plurality of IGBT cells. The temperature sensing module includes a temperature sensor, an anode pad, a cathode pad, and a metal lead. The temperature sensor and at least a part of the metal lead are located in the gate finger structure and are insulated from the gate finger structure.

Abstract: This application provides an insulated gate bipolar transistor, a motor control unit, and a vehicle. The insulated gate bipolar transistor includes three device structure feature layers that are laminated. An IGBT device structure feature layer (10) and an RC-IGBT device structure feature layer (30) are respectively arranged on two sides of an SJ device structure feature layer (20). The RC-IGBT device structure feature layer (30) includes a collector (12) and a drain (13) that are disposed at a same layer. The insulated gate bipolar transistor further includes a first metal electrode (15) laminated with and electrically connected to the collector (12), and a second metal electrode (14) laminated with and electrically connected to the drain (13), and the first metal electrode (15) is electrically isolated from the second metal electrode (14).