Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

Abstract: A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one feature. The method includes forming the nucleation layer via a cyclic vapor deposition process. The cyclic vapor deposition process includes forming a portion of the nucleation layer and then exposing the exposing the nucleation layer a chemical vapor transport (CVT) process to remove impurities from the portion of the nucleation layer. The CVT process may be performed at a temperature of 400 degrees Celsius or less and comprises forming a plasma from a processing gas comprising greater than or equal to 90% of hydrogen gas of a total flow of hydrogen gas and oxygen.

Abstract: Apparatus that forms low resistivity tungsten film on substrates. In some embodiments, the apparatus may provide reduced resistivity of tungsten by being configured to generate a plasma in a processing volume of a physical vapor deposition (PVD) chamber with a process gas of krypton and using an RF power with a frequency of approximately 60 MHz, apply bias power at frequency of approximately 13.56 MHz to a substrate, and sputter a tungsten target to deposit a tungsten thin film on the substrate. At least approximately 90% of the deposited tungsten thin film has a <110> crystalline orientation plane approximately parallel to a top surface of the substrate.

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Apparatus that forms low resistivity tungsten film on substrates. In some embodiments, the apparatus may provide reduced resistivity of tungsten by being configured to generate a plasma in a processing volume of a physical vapor deposition (PVD) chamber with a process gas of krypton and using an RF power with a frequency of approximately 60 MHz, apply bias power at frequency of approximately 13.56 MHz to a substrate, and sputter a tungsten target to deposit a tungsten thin film on the substrate. At least approximately 90% of the deposited tungsten thin film has a <110> crystalline orientation plane approximately parallel to a top surface of the substrate.

Abstract: Method and apparatus that forms low resistivity tungsten film on substrates. In some embodiments, a method of reducing resistivity of tungsten includes generating a plasma in a processing volume of a physical vapor deposition (PVD) chamber with a process gas of krypton and using an RF power with a frequency of approximately 60 MHz and a magnetron, applying bias power at frequency of approximately 13.56 MHz to a substrate, and sputtering a tungsten target to deposit a tungsten thin film on the substrate. At least approximately 90% of the deposited tungsten thin film has a <110> crystalline orientation plane approximately parallel to a top surface of the substrate.

Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: Method and apparatus that forms low resistivity tungsten film on substrates. In some embodiments, a method of reducing resistivity of tungsten includes generating a plasma in a processing volume of a physical vapor deposition (PVD) chamber with a process gas of krypton and using an RF power with a frequency of approximately 60 MHz and a magnetron, applying bias power at frequency of approximately 13.56 MHz to a substrate, and sputtering a tungsten target to deposit a tungsten thin film on the substrate. At least approximately 90% of the deposited tungsten thin film has a <110> crystalline orientation plane approximately parallel to a top surface of the substrate.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: Methods for processing a substrate are provided herein. The method, for example, includes selectively depositing a first layer of metal within at least one feature on a substrate; depositing a second layer of metal atop the first layer of metal and at least on sidewalls defining the at least one feature; depositing a third layer of metal atop the second layer of metal and within the feature to at least completely fill the at least one feature; and removing some of the second layer of metal or some of the second layer of metal and some of the third layer of metal so that remaining portions of the second layer of metal and the third layer of metal are flush with a top surface of the at least one feature.

Abstract: Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature disposed in a substrate includes (a) depositing a metal within the feature to a first predetermined thickness in a first process chamber; (b) depositing the metal within the feature to a second predetermined thickness in a second process chamber; (c) etching the metal deposited in (b) to remove an overhang of the metal at a top of the feature in a third process chamber different than the first and second process chambers; and (d) subsequent to (c), filling the feature with the metal in a fourth process chamber different than the first and third process chambers.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.