Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.

Abstract: A fusion protein is disclosed. The fusion protein of the invention comprises an Fc fragment of an immunoglobulin G and a bioactive molecule, wherein the Fc is a single chain Fc. The amino acids in the hinge of the Fc is mutated, substituted, or deleted so that the hinge of Fc cannot form disulfide bonds. Methods for producing and using the fusion protein of the invention are also provided.

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: An object detection assistant system includes a memory and a processor. The processor is coupled to the memory. The memory stores one or more commands. The processor accesses and executes one or more commands of the memory. One or more commands include inputting a detection result parameter output by an object detection neural network for object detection of an image to an assistant neural network to output a first correction coefficient after processing by the assistant neural network, where the detection result parameter includes object information and a first confidence; inputting the first correction coefficient and detection result parameters to a Bayesian classifier to output a second correction coefficient; and adjusting the first confidence according to the second correction coefficient to obtain second confidence, and the second confidence being taken as the first confidence of the adjusted detection result parameter.

Abstract: A stretchable pixel array substrate includes a base, pixel structures and a gate driving circuit electrically connected to the pixel structures. The base has an active area and a peripheral area outside the active area. The peripheral area has openings to define first islands, second islands and first bridges of the peripheral area. An area of each of the first islands is greater than an area of each of the second islands. At least a part of the first bridges is connected between the first islands and the second islands. The pixel structures are disposed on the active area of the base. The gate driving circuit includes first parts disposed on the first islands and second parts disposed on the second islands and electrically connected to the first parts.

Abstract: A catalytic composition for preparing a polyethylene terephthalate (PET) resin is provided. The catalytic composition comprises a polycondensation catalyst and cesium tungsten oxide (CsxWO3-yCly), and 0<x?1 and 0?y?0.5. A PET resin prepared by the catalytic composition above is also provided. The PET resin comprises 2-80 ppm of cesium tungsten oxide. This catalytic composition can solve the problems of slow solid-state polymerization rate of the PET preparation and thus the long preparation time, as well as yellowing. Moreover, the PET resin can absorb infrared radiation.

Abstract: The disclosure provides a method for obtaining optimal operating condition of a resistive random access memory (RRAM). The method includes: retrieving an RRAM chip and performing a forming operation and an initial reset operation thereto based on a first operating condition; segmenting the RRAM chip into blocks; performing a set operation to each of the blocks based on various operating voltages; obtaining a fail bit value of each of the blocks; generating an operating characteristic curve related to the RRAM chip based on the fail bit value of each of the blocks and the operating voltages, wherein the operating characteristic curve has a lowest fail bit value and an operating voltage window; and when the lowest fail bit value and the operating voltage window satisfy a first condition and a second condition, respectively, determining the first operating condition is an optimal operating condition of the RRAM chip.

Abstract: A catalytic composition for preparing a polyethylene terephthalate (PET) resin is provided. The catalytic composition comprises a polycondensation catalyst and cesium tungsten oxide (CsxWO3-yCly), and 0<x?1 and 0?y?0.5. A PET resin prepared by the catalytic composition above is also provided. The PET resin comprises 2-80 ppm of cesium tungsten oxide. This catalytic composition can solve the problems of slow solid-state polymerization rate of the PET preparation and thus the long preparation time, as well as yellowing. Moreover, the PET resin can absorb infrared radiation.

Abstract: The invention relates to a safety agglutination glass structure, comprising two glass substrates and a heat insulating adhesive membrane. The heat insulating adhesive membrane constituted of heat insulating particles and a colloid material is disposed between the two glass substrates. Therefore, the two glass substrates can combine together by heating and pressurizing for the purpose of simplifying processing procedures, reducing the costs and preventing distortion.