Abstract: Disclosed are a frequency multiplier, a signal transmitter and a radar chip. The frequency multiplier includes a signal generator that is configured to receive an FMCW signal and output a square wave signal at a frequency same as a frequency of the FMCW signal; and a third harmonic amplifier that is coupled to the signal generator and is configured to amplify a third harmonic wave in the square wave signal and output a frequency-tripled FMCW signal. The above-mentioned solution can improve the generation efficiency of the frequency-tripled signal.

Abstract: A phase shifting system, a chip, and a radar sensor are provided. A respective transmission line phase-shifting unit is configured to receive at least one phase shifting control signal and to shift a phase of a RF signal by a first phase or a second phase. Each transmission line phase-shifting unit includes a first group of transmission lines and a second group of transmission lines. At least some transmission lines in the first group of transmission lines of each transmission line phase-shifting unit are physically isolated from at least some transmission lines in the first group of transmission lines of an adjacent transmission line phase-shifting unit and transmission lines of the second group of transmission lines of each transmission line phase-shifting unit are coupled to respective transmission lines of the second group of transmission lines of an adjacent transmission line phase-shifting unit.

Abstract: A transmission line phase shifter, a system, a chip, and a radar sensor are provided. The transmission line phase shifter includes at least one transmission line phase-shifting unit. A respective transmission line phase-shifting unit includes a first pair of differential transmission lines, a second pair of differential transmission lines, and a phase adjusting circuit. The phase adjusting circuit is configured to adjust electrical parameters of a transmission path where at least one pair of transmission lines of the first pair of differential transmission lines and the second pair of differential transmission lines is located according to at least one phase shifting control signal received, so as to enable that a RF signal output from the respective transmission line phase-shifting unit has a phase shift of a first phase or a second phase relative to an input RF signal of the respective transmission line phase-shifting unit.

Abstract: A transmission line phase shifter, a chip, and a radar sensor are provided. The transmission line phase shifter includes at least one transmission line phase-shifting unit. At a calibration stage, a preset number of transmission line phase-shifting units are configured to be in a state of a first phase or in a state of a second phase and configured to output an output RF signal, such that phase calibration information of each transmission line phase-shifting unit is determinable. At an operation stage, the phase adjusting circuit of the respective transmission line phase-shifting unit is configured to receive a corresponding phase shifting control signal and to adjust the respective transmission line phase-shifting unit, to enable the respective transmission line phase-shifting unit to shift a phase of an input RF signal by a calibrated first phase or a calibrated second phase.

Abstract: A radio frequency (RF) inverter, a transmission line phase shifter, a system, a chip, and a radar sensor are provided. The RF inverter includes an inductance circuit and a first phase adjusting circuit that both are arranged symmetrically along a same symmetry axis. The inductance circuit includes a single-ended signal interface and a differential signal interface. The first phase adjusting circuit includes two controlled switches, and each controlled switch is connected between the ground wire and a corresponding ground terminal of a pair of ground terminals in the single-ended signal interface, to enable the inductance circuit to perform in-phase or inverting phase shifting on a received RF signal.

Abstract: The present invention discloses a chemical mechanical polishing slurry, and the chemical mechanical polishing slurry comprises silica abrasive particles and accelerating agents, wherein the accelerating agents are selected from pyridine compound, piperidine compound, pyrrolidine compound or pyrrole compound and their derivatives, which have one or more carboxyl groups, and pyrimidine compound and its derivatives, which have one or more amino groups. The chemical mechanical polishing slurry can simultaneously increase the removal rate of both silicon nitride and polysilicon.

Abstract: The sensing system includes at least one chip branch. In the chip branch, a clock circuit of each sensing chip integrates the received working clock signal to obtain stable clock signal that has a relative high frequency to be subjected to frequency dividing, and a frequency dividing circuit performs frequency dividing processing on the clock signal to obtain a working clock signal required by a next-stage sensing chip. In the cascade structure, a clock source only needs to satisfy the driving requirement of a first-stage sensing chip, and the working clock signal required by each of other sensing chips is provided by a previous-stage sensing chip, such that the problem that the number of sensing chips connected in series in the chip branch is limited by the driving capability of the clock source is solved, and the applicability of the sensing system is widened.

Abstract: A delay calibration circuit and method, an analog-to-digital converter, a radar sensor, and a device are provided. The delay calibration circuit monitors a timing relationship between signals in a chip in real time to extract PVT information, dynamically adjusts conversion timing of an asynchronous SAR ADC, maximally utilizes an available conversion time in each cycle of the asynchronous SAR ADC, improves the robustness of the asynchronous SAR ADC, and does not affect the normal operation of the asynchronous SAR ADC.

Abstract: A radar system and control method thereof is disclosed. The radar system comprises a plurality of radar units, each comprising: one or more radio frequency (RF) channels configured to receive a reflected signal and then generate an analog input signal according to the reflected signal; and a processing module connected with all the RF channels and configured to sample the analog input signal to obtain a digital signal and perform the first digital signal processing on the digital signal to obtain intermediate data, wherein when the plurality of radar units work jointly, a designated radar unit performs the second digital signal processing on the plurality of intermediate data provided by the plurality of radar units, thereby obtaining result data of the radar system.

Abstract: A chemical mechanical polishing slurry, including silicon dioxide particles, a nitrogen-containing heterocyclic compound having one or more carboxy group(s), and an ethoxylated butoxylated alky alcohol, and use of the chemical mechanical polishing slurry in the polishing silicon oxide, polysilicon, and silicon nitride. Polishing rate for silicon nitride using the polishing slurry is much higher than that for silicon oxide and polysilicon. The polishing slurry can be applied to chemical mechanical polishing in which silicon oxide/polysilicon is used as the stop layer, and can be used to control the amount of oxide and polysilicon removed from the substrate surface during polishing.

Abstract: A chemical-mechanical polishing slurry having high Silicon Nitride removal rate selectivity includes abrasive particles and a compound containing one or more carboxyl groups. The polishing slurry has high SiN removal rate, low TEOS removal rate, and high removal rate selectivity of SiN to TEOS. The polishing slurry can significantly reduce the defects on Oxide surface which has an excellent market application prospect.

Abstract: The present invention discloses a chemical mechanical polishing slurry, and the chemical mechanical polishing slurry comprises silica abrasive particles and accelerating agents, wherein the accelerating agents are selected from pyridine compound, piperidine compound, pyrrolidine compound or pyrrole compound and their derivatives, which have one or more carboxyl groups, and pyrimidine compound and its derivatives, which have one or more amino groups. The chemical mechanical polishing slurry can simultaneously increase the removal rate of both silicon nitride and polysilicon.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: A chemical-mechanical polishing slurry having high Silicon Nitride removal rate selectivity includes abrasive particles and a compound containing one or more carboxyl groups. The polishing slurry has high SiN removal rate, low TEOS removal rate, and high removal rate selectivity of SiN to TEOS. The polishing slurry can significatntly reduce the defects on Oxide surface which has an excellent market application prospect.

Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.