Abstract: Embodiments of this application provide a clock phase recovery apparatus and method, and a chip. The clock phase recovery apparatus includes an ADC, a dispersion compensation unit, a digital interpolator, a MIMO equalization unit, and a clock offset phase obtaining unit. The ADC is connected to the dispersion compensation unit, and the dispersion compensation unit is connected to a first input end of the digital interpolator. An output end of the digital interpolator is connected to an input end of the MIMO equalization unit, and an output end of the MIMO equalization unit is connected to an input end of the clock offset phase obtaining unit. The digital interpolator is configured to adjust, based on first offset phase information output by the clock offset phase obtaining unit, a dispersion-compensated signal output by the dispersion compensation unit.

Abstract: Embodiments of this application provide a clock phase recovery apparatus and method, and a chip. The clock phase recovery apparatus includes an ADC, a dispersion compensation unit, a digital interpolator, a MIMO equalization unit, and a clock offset phase obtaining unit. The ADC is connected to the dispersion compensation unit, and the dispersion compensation unit is connected to a first input end of the digital interpolator. An output end of the digital interpolator is connected to an input end of the MIMO equalization unit, and an output end of the MIMO equalization unit is connected to an input end of the clock offset phase obtaining unit. The digital interpolator is configured to adjust, based on first offset phase information output by the clock offset phase obtaining unit, a dispersion-compensated signal output by the dispersion compensation unit.

Abstract: Embodiments of this application provide a method for obtaining a phase detection signal in a clock recovery circuit and a phase detector, configured to obtain a correct phase detection signal. A phase detector obtains sampling sequences sent by an analog to digital converter ADC, where the sampling sequences are obtained by the ADC by sampling, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; the phase detector calculates a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, where the first location and the second location are locations of a starting point of the training sequence in the sampling sequences; and the phase detector obtains a phase detection signal based on a difference parameter of the first location and the second location.

Abstract: Embodiments of this application provide a method for obtaining a phase detection signal in a clock recovery circuit and a phase detector, configured to obtain a correct phase detection signal. A phase detector obtains sampling sequences sent by an analog to digital converter ADC, where the sampling sequences are obtained by the ADC by sampling, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; the phase detector calculates a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, where the first location and the second location are locations of a starting point of the training sequence in the sampling sequences; and the phase detector obtains a phase detection signal based on a difference parameter of the first location and the second location.

Abstract: A microwave photonics based signal receiving device includes a signal generation module, a first Mach-Zehnder modulator, a dispersion module, a second Mach-Zehnder modulator, and a signal conversion module. The signal receiving device simplifies a structure of the signal receiving device by adopting quadrature demodulation. The signal receiving device demodulates a high-order modulation signal and flexibly adjusts a microwave carrier frequency.

Abstract: A method, an apparatus, and a system for feedback control of a coherent receiver are provided. The method for feedback control of the coherent receiver includes: obtaining a feedback control quantity according to a digital signal converted by an Analog-to-Digital Converter (ADC); and adjusting a signal amplitude output by a Transimpedance Amplifier (TIA) and a direct current component of an offset T device according to the feedback control quantity, until an analog signal input into the ADC is in a sampling range of the ADC, where the TIA is serially connected to the offset T device and then is connected to the ADC. Present invention has the following advantages: enabling the analog signal to adapt to the ADC sampling best, maximizing an effective information quantity sampled by the ADC and better supporting subsequent processing of a Digital Signal Processing (DSP) unit, thereby improving a coherent receiving performance.

Abstract: A method, an apparatus, and a system for feedback control of a coherent receiver are provided. The method for feedback control of the coherent receiver includes: obtaining a feedback control quantity according to a digital signal converted by an Analog-to-Digital Converter (ADC); and adjusting a signal amplitude output by a Transimpedance Amplifier (TIA) and a direct current component of an offset T device according to the feedback control quantity, until an analog signal input into the ADC is in a sampling range of the ADC, where the TIA is serially connected to the offset T device and then is connected to the ADC. Present invention has the following advantages: enabling the analog signal to adapt to the ADC sampling best, maximizing an effective information quantity sampled by the ADC and better supporting subsequent processing of a Digital Signal Processing (DSP) unit, thereby improving a coherent receiving performance.