Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a second region, and word lines each extending from the first region into at least a portion of the second region. At least one word line pick-up structure includes multiple sections each electrically connected to a different word line.

Abstract: Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: A federated learning training method is performed by a server. The method comprises: receiving gradient information of a labeled sample of each client sent by each client; according to the gradient information sent by each client, obtaining target gradient information belonging to a same labeled sample; determining a client to which each labeled sample belongs; and sending, to a client to which the same labeled sample belongs, the target gradient information corresponding to the same labeled sample.

Abstract: A resonance control method for differentiated phase correction under asymmetric positive and negative bilateral frequency domains includes a differentiated phase correction resonance control link with an independent phase correction angle at each resonance point, a decoupling link and a delay compensation link. As a high power converter has the characteristic of asymmetric positive and negative bilateral frequency domains under resonance control with decoupling, stability margin of a control link is enhanced while a negative-sequence current suppression capability is realized by means of differentiated phase correction at positive and negative resonance poles.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor.

Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device comprises a first semiconductor structure including a core region, a spacer region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure comprises a memory stack on a semiconductor layer in the core region, a first periphery circuit on the semiconductor layer in the periphery region, and a spacer structure in the spacer region to separate the memory stack and the first periphery circuit. The second semiconductor structure is connected to the first semiconductor structure.

Abstract: In a method for training a federated learning model, a server obtains a target split mode corresponding to a training node in response to determining that the training node satisfies a preset splitting condition. The server notifies a client to perform, based on the target split mode, node splitting. The server performs a next round of training by taking a left subtree node generated by performing the node splitting as a new training node until an updated training node does not satisfy the preset splitting condition. The server performs a next round of training by taking another non-leaf node of the boosting tree as a new training node. The server stops training and generates a target federated learning model in response to determining that a node dataset of the plurality of boosting trees is empty.

Abstract: An experimental system a method for studying jet impact characteristics at a core outlet of a fast reactor are provided. The system includes a jet impact main loop including a water storage tank, plunger pumps, a filter, preheaters, a jet impact chamber, a heat regenerator, a condenser, valves, flow meters and pipelines connecting these facilities; a cooling loop including cooling tower, a cooling pump, a regulating valve and a flow meter; and a makeup water loop including a deionized water machine, a makeup water tank and a plunger pump. Water in the water storage tank flows to the heat regenerator via the plunger pump, is preliminarily heated by the heat regenerator and then is divided into three branches to flow to the jet impact container.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: The present invention discloses a method and device for formulating a coordinated action strategy of SSTS and DVR for voltage sag mitigation. The influence of voltage sag on a whole industrial process of a sensitive user is analyzed, and the sensitive loads of SSTS and DVR which satisfy a governance need are grouped; a practical governance scenario of installing a plurality of DVR is considered to install a minimum-capacity DVR to realize a target of a minimum interruption probability of the whole industrial process of the user; an optimal coordinated governance solution of SSTS and DVR based on sensitive load grouping is proposed; a classification result is obtained for duration time at a time when a voltage sag event occurs through a decision tree constructed based on historical data.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: The present disclosure discloses a phase-change flame-retardant fiber material for thermal management of a lithium ion battery in a closed space and a preparation method. The phase-change flame-retardant fiber material is prepared in a coaxial electrostatic spinning manner and includes a composite phase-change fiber material PASA-TPU at a core part and a flame-retardant fiber material TB-PAN wrapping a surface of the core part. The composite phase-change fiber material is well wrapped with the flame-retardant fiber material, and the lithium ion battery wrapping the whole phase-change flame-retardant fiber material in the closed space is subjected to charge-discharge cycle; the result shows that the surface temperature of the battery can be effectively reduced by about 20° C.