Abstract: Systems and methods for a memory structure are described for increasing the throughput of double precision operations. Broadly, the present invention utilizes a novel memory system to process double precision data in a single memory access. In accordance with one embodiment, a method for increasing throughput of arithmetic operations on double precision data by reducing the number of memory accesses comprising: retrieving a double precision value from a memory, wherein the double precision value is comprised of a high word and a low word, wherein the double precision value is retrieved in a single memory access; selecting a word within the double precision value, wherein the portion selected is a single precision value; multiplying the word with a single precision operand to generate a single precision product; adding the product to a double precision operand to produce a double precision result; and forwarding the double precision result back to memory for storage.

Abstract: The present invention generally relates to echo cancellation over an asymmetric transmission and receiving spectra. An apparatus is provided having a transmit path and a receive path, with an adaptive echo canceler disposed therebetween, for communicating data within a first bandwidth and a second bandwidth respectively. A first decimator is disposed between the transmit path and the echo canceler circuit and filters an incoming signal having a first sampling rate and emits a signal output at a second, reduced sampling rate. A second decimator is disposed along said receive path and filters an incoming signal and emits a signal output at a reduced sampling rate. An adder is disposed to subtract the output of the adaptive echo canceler from output of the second decimator to generate a received signal that is substantially free of echo.

Abstract: Disclosed is a system and method for signal conditioning and equalization in the time domain, preferably in a discrete multi-tone (DMT) modem. The system preferably includes a processor operating according to operating logic stored on a memory although a dedicated logical circuit may be employed. The operating logic includes logic executing the function of a low pass filter having a predetermined cutoff frequency configured to process a digitized data signal having a first sample rate f0, producing a filtered data signal at a second sample rate f1. The operating logic further includes logic which executes the function of a time domain equalizer, the time domain equalizer being configured to process the filtered signal to shorten the impulse response of the channel while at the same time, the time domain equalizer down-samples the filtered signal from the second sample rate f1, to a third sample rate f2 for further processing in the frequency domain.