Abstract: Transcription factors (TFs) represent a major class of therapeutic targets for the treatment of human diseases including cancer. Although the biological function and even crystal structure of many TFs have been clearly elucidated, there is still no viable approach to target the majority of TFs, thus rendering them undruggable for decades. PROTACs (PROteolysis TArgeting Chimeras) have emerged as a powerful tool for the pharmaceutical development since the effect of PROTACs largely relies on engineered protein-protein interaction to aid the degradation of targets by the ubiquitin-proteasome system (UPS). The present disclosure provides a DNA-PROTAC platform for targeted degraders of individual TFs of interest. These DNA based Transcription Factor targetting PROTACS (or “TF-PROTACS”) may provide specificity to TF degradation based on the conserved DNA-binding motifs of respective TFs.

Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.

Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.

Abstract: Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.

Abstract: Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.

Abstract: An integrated circuit for supporting a high-speed communications link. The integrated circuit may include equalization and hybrid phase detection circuitry configured to perform clock data recovery (CDR) for high-order pulse amplitude modulated (PAM) signals. The phase detector circuit includes partial oversampling sampling circuitry that generates edge samples an incoming PAM signal and Baud rate sampling circuitry that generates error and data samples on the PAM signals. Edge, data, and error samples may be passed to error minimization circuitry within an adaptation circuit that may dynamically compute contributions to a weighted phase error by oversampling and Baud rate components. The adaptation circuit may use the weighted phase error to adjust the phase of a recovered clock signal used to recover data transmitted through the high speed communications link.

Abstract: An integrated circuit for supporting a high-speed communications link is provided. The integrated circuit may include equalization circuitry having a continuous time linear equalizer (CTLE) circuit, a decision feedback equalizer (DFE) circuit, and associated adaptation logic for controlling the CTLE circuit and the DFE circuit. The adaptation logic may include an error minimization adaptation circuit operable to generate at least a first post-cursor value, a signal amplitude detection circuit operable to generate a main cursor value, and a CTLE adaptation circuit configured to compute a ratio between the first post-cursor value and the main cursor value. The CTLE adaptation circuit may compare the computed ratio to predetermined values to determine whether or not to adjust the peaking gain of the CTLE circuit to help minimize inter-symbol interference for signals traveling through the high-speed communications link.

Abstract: An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

Abstract: An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.

Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Abstract: A receiver comprises equalization circuitry implementing at least first and second gain adaptation loops associated with respective first and second frequency bands. The equalization circuitry in one aspect is operative to identify a pattern in a portion of a received serial data stream, and to perform gain adaptation for the receiver utilizing a particular one of the gain adaptation loops responsive to the identified pattern. For example, the gain adaptation may be performed utilizing a low frequency gain adaptation loop if the detected pattern is of a first type generally associated with a low frequency band, and may be performed utilizing a high frequency gain adaptation loop if the detected pattern is of a second type generally associated with a high frequency band. In other aspects, the first and second gain adaptation loops may be activated in a particular serial order or in parallel.

Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.

Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Abstract: A block of symbols are decoded using iterative belief propagation. A set of belief registers store beliefs that a corresponding symbol in the block has a certain value. Check processors determine output check-to-bit messages from input bit-to-check messages by message-update rules. Link processors connect the set of belief registers to the check processors. Each link processor has an associated message register. Messages and beliefs are passed between the set of belief registers and the check processors via the link processors for a predetermined number of iterations while updating the beliefs to decode the block of symbols based on the beliefs at termination.