Patents by Inventor Wenyi Li
Wenyi Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150211716Abstract: The invention proposes a lighting device (250). The lighting device (250) for road lighting comprises a lighting module and a control module coupled to the lighting module, and configured to control the lighting module to radiate a first light beam (221) towards a first direction to generate a first lighting pattern on the road surface (B), when a first predetermined condition is satisfied, and to control the lighting module to radiate a second light beam (231) towards a second direction to generate a second lighting pattern on the road surface (A), when a second predetermined condition is satisfied, wherein the first direction is oriented to go along the traffic direction and the second direction is oriented to go opposite the traffic direction.Type: ApplicationFiled: July 5, 2013Publication date: July 30, 2015Inventors: Wenyi Li, Wenting Cheng
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Publication number: 20150167930Abstract: There is provided a lighting apparatus and a method for reducing discomfort glare. The method comprises a step of providing a first portion of light radiation in a first incident angle range; and another step of providing a second portion of light radiation in a second incident angle range consecutive to the first incident angle range. The first incident angle range is greater than the second incident angle range viewed from a vertically downward direction of a light source emitting the light radiation, and the correlated color temperature of the first portion of light radiation is lower than that of the second portion of light radiation.Type: ApplicationFiled: May 21, 2013Publication date: June 18, 2015Inventors: Xiaoyan Zhu, Wenyi Li, Shitao Deng, Miao Zhang
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Patent number: 8932928Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.Type: GrantFiled: May 12, 2014Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Peilin Wang, Edouard D. de Fresart, Wenyi Li
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Publication number: 20140342518Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.Type: ApplicationFiled: May 12, 2014Publication date: November 20, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Peilin Wang, Edouard D. de Fresart, Wenyi Li
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Publication number: 20140313736Abstract: The invention discloses a lighting device for a road lighting luminaire and a lighting luminaire comprising the lighting device. The lighting device comprises a reflector (301), which comprises a reflecting surface (3011) formed by revolving a parabolic curve around a first axis (y) through a predetermined angle, wherein said parabolic curve has an aperture at its vertex, said first axis axis being co-planar with said parabolic curve, and extending substantially perpendicularly to the axis (x) of symmetry of said parabolic curve, and being located at or outside of said aperture of said parabolic curve. The lighting device further comprises a LED light source (302), which is disposed at an entry to said reflecting surface, with said entry corresponding to said aperture of said parabolic curve. In this way, light distribution can be controlled in the same way in any plane containing the first axis within the range of the predetermined angle.Type: ApplicationFiled: October 23, 2012Publication date: October 23, 2014Inventors: Wenyi Li, Shitao Deng, Xiaoyan Zhu
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Patent number: 8759909Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.Type: GrantFiled: September 11, 2012Date of Patent: June 24, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Peilin Wang, Edouard D. de Fresart, Wenyi Li
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Publication number: 20140159146Abstract: A trench gate transistor is formed from a semiconductor substrate with its upper surface covered in an oxide dielectric layer. The trench gate transistor has a drain region, a body region, source region and a trench lined with a gate insulator that electrically insulates a conductive gate electrode formed in the trench from the body region. The body region has a sloping upper surface that extends away from the trench towards the drain region. The sloping upper surface is formed by exposing the oxide dielectric layer to an oxidized atmosphere, through an opening in a mask, so as to form a dielectric region. The dielectric region includes the oxide dielectric layer and a sacrificial area of the semiconductor substrate.Type: ApplicationFiled: November 5, 2013Publication date: June 12, 2014Inventors: Peilin Wang, EDOUARD DE FRESART, WENYI LI
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Publication number: 20140070313Abstract: A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Peilin Wang, Jingjing Chen, Edouard D. de Fresart, Pon Sung Ku, Wenyi Li, Ganming Qin
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Publication number: 20130299898Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.Type: ApplicationFiled: September 11, 2012Publication date: November 14, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Peilin Wang, Edouard D. de Fresart, Wenyi Li
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Publication number: 20130012375Abstract: Disclosed herein is a process for preparation of an ultra high molecular weight polyethylene catalyst, comprising: (1) under inert atmosphere, dispersing a magnesium halide in an inert solvent; (2) adding an alcohol to react with the magnesium halide, to form a solution or dispersion of a magnesium halide-alcohol adduct; (3) adding an alkyl aluminum halide to react with the magnesium halide-alcohol adduct, to form an intermediate product; (4) optionally, subjecting the intermediate product to an ultrasonic wave treatment; (5) adding a titanium compound to perform Ti-supporting reaction; (6) optionally, subjecting the reaction mixture from step (5) to an ultrasonic wave treatment; and (7) recovering solid particles, to obtain the ultra high molecular weight polyethylene catalyst, wherein at least one of steps (4) and (6) is present.Type: ApplicationFiled: July 3, 2012Publication date: January 10, 2013Inventors: Liuzhong Li, Jianyong Zhou, Xiaoqing Li, Xiaolong Bi, Wenyi Li, Yongling Yu, Jie Yan, Lifang Qi, Gongtao Li, Dapeng Fan, Xiao Xu, Xiaojing Pei
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Publication number: 20100213545Abstract: The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.Type: ApplicationFiled: May 15, 2008Publication date: August 26, 2010Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventors: Ching Tee Elizabeth Kho, Mee Guoh Michael Tiong, Kia Yaw Kee, Wen Jun Li, Wenyi Li, Michael May, Chean Chian Alain Liew
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Patent number: 7532324Abstract: This invention belongs to the luminous flux measurement field, and especially relates to the equipment and method for LED's total luminous flux measurement with a narrow beam standard light source. The system for LED's total luminous flux measurement with a narrow beam standard light source in this invention comprises an integrating sphere, the light source, a narrow aperture fiber, a spectrometer and a driver for the light source. The light source is lighted by the driver. The narrow beam standard light source (both luminous flux standard and spectrum standard) is placed on the interior surface of integrating sphere, there is not any baffle in the sphere, and a narrow aperture fiber transfers the light to a multi-channel spectrometer which measures the spectrum distribution of LED and calculates its total luminous flux. The equipment in this invention is easy to use, has small error and low cost, and can achieve accurate results for LED's total luminous flux.Type: GrantFiled: October 23, 2007Date of Patent: May 12, 2009Assignee: Fu Dan UniversityInventors: Muqing Liu, Xiaoli Zhou, Wenyi Li, Wanlu Zhang, Chuan Yuan
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Publication number: 20080129996Abstract: This invention belongs to the luminous flux measurement field, and especially relates to the equipment and method for LED's total luminous flux measurement with a narrow beam standard light source. The system for LED's total luminous flux measurement with a narrow beam standard light source in this invention comprises an integrating sphere, the light source, a narrow aperture fiber, a spectrometer and a driver for the light source. The light source is lighted by the driver. The narrow beam standard light source (both luminous flux standard and spectrum standard) is placed on the interior surface of integrating sphere, there is not any baffle in the sphere, and a narrow aperture fiber transfers the light to a multi-channel spectrometer which measures the spectrum distribution of LED and calculates its total luminous flux. The equipment in this invention is easy to use, has small error and low cost, and can achieve accurate results for LED's total luminous flux.Type: ApplicationFiled: October 23, 2007Publication date: June 5, 2008Applicant: FU DAN UNIVERSITYInventors: Muqing Liu, Xiaoli Zhou, Wenyi Li, Wanlu Zhang, Chuan Yuan