Abstract: Driver circuitry for memory controller circuitry includes level shifter circuitry, inverter circuitry, and output circuitry. The level shifter circuitry receives an input data signal and outputs a first level shifted data signal and a second level shifted data signal based on the input data signal. The inverter circuitry is connected to the level shifter circuitry, receives the first level shifted data signal and the second level shifted data signal, and outputs a first inverted data signal via a first output node and a second inverted data signal via a second output node. The inverter circuitry includes mitigation circuitry coupled to the first output node and the second output node and alters one or more of the first inverted data signal and the second inverted data signal. The output circuitry outputs an output data signal based on the first inverted data signal and the second inverted data signal.

Abstract: A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

Abstract: An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground node, the output transistor including a gate; first, second, and third stacked transistor pairs each serially coupled between the output node and the ground node, each transistor of the first, second, and third stacked transistor pairs including a gate; and switch circuits configured to selectively couple: the gates of the first and second stacked transistor pairs to the second node; and the gate of the output transistor to the first node.

Abstract: A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change-of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches.

Abstract: A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one latch stage are connected to the corresponding differential D-inputs of the next latch stage. For even numbers of latch stages, the differential clock inputs of each are connected together and alternately to the divider clock input and its complement. The last differential Q-output is returned and cross-connected to the differential D-inputs of the first latch stage. For odd numbers of latch stages, the differential clock inputs of each are respectively connected in parallel to the divider clock input and its complement. The last differential Q-output is returned and straight-connected to the differential D-inputs of the first latch stage.

Abstract: A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.

Abstract: The invention relates to a multi-phase inverter ring oscillator generating multiple output signals arranged in groups of four. In an example embodiment, an even number of inverters are coupled together in a cascaded series, each inverter has an input and an output, the output of one inverter is coupled to the input of a next sequential one of the inverters. There are a corresponding number of cross-coupled transistors. Each cross-coupled transistor couples the input of one inverter to the output of the next sequential one of the inverters. In a particular example embodiment, a four-phase inverter ring oscillator generates four output signals that are shifted 90° in phase and may be used to generate 50% duty cycle clocks.

Abstract: A semiconductor test chip has an array of active semiconductor devices to be individually tested, a number of test lines for connection to external test circuitry, an enabling circuit associated with each device for selectively connecting it to the test lines, an input for receiving an instruction identifying a device that it is desired to test, and a decoder incorporated into the chip for receiving the instruction from the input. The decoder is connected by enabling lines to the individual test devices so that on receipt of an instruction the decoder enables the identified test device such that it becomes connected to the test lines. This circuit is more efficient and less cumbersome than the prior art.