Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: A network identity protection method and device, and electronic equipment and a computer-readable storage medium.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: An automated palletizer for building a mixed case pallet comprising of a case infeed that feeds mixed cases provides an input queue feed sequence of mixed cases to at least one pallet building robot that is communicably connected to the case infeed and accesses the mixed cases of the input queue feed sequence. The robot receives mixed cases in the input queue feed and place mixed cases according to the input queue feed so as to effect building the mixed case pallet at a predetermined and substantially steady placement rate which the controller is communicably connected to the case infeed and the at least one pallet building robot. The controller is designed to generate a complete and stable mixed case arrangement plan that completes a predetermined whole part of the mixed case pallet that describes a predetermined planned location and pose for each case of the mixed case arrangement plan.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: A compound profiling forging method for a wind turbine main shaft includes: making a billet into a flat square billet, returning the billet into a furnace and holding a temperature at 1250° C.; preliminary punching, including: upsetting and drawing out the billet twice, and carrying out punching and rolling; preparing a piercing punch and a punching block, putting the billet in the punching block, putting the piercing punch into a hole of the billet, and operating an oil press to press the piercing punch to be flush with the billet; heating the billet, holding a temperature at 850° C., putting the billet in the punching block, preparing a female die and a punch, and inserting the piercing punch into an inner hole of the billet to carry out flange upsetting; and drawing out the shaft body of the billet in sequence, with a forging temperature range of 850-1250° C.

Abstract: An automated palletizer for building a mixed case pallet, the automated palletizer including a case infeed that feeds mixed cases to provide an input queue feed sequence of mixed cases. At least one pallet building robot communicably connected to the case infeed and configured to receive the mixed cases in the input queue feed sequence of mixed cases, and place the mixed cases according to and dependent on the input queue feed sequence of mixed cases so as to effect building the mixed case pallet at a predetermined substantially steady placement rate. A controller communicably connected to the case infeed and at least one pallet building robot, and being configured so as to generate a complete and stable mixed case arrangement plan that completes at least a predetermined whole part of the mixed case pallet and that describes a predetermined planned location and pose for each case.

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

Abstract: The present application discloses an N-type MOSFET, comprising: a gate structure formed on the surface of a semiconductor substrate; an embedded epitaxial layer formed on each of the two sides of the gate structure, wherein the embedded epitaxial layer fills in a groove, and the groove is formed in the semiconductor substrate; and a source region and a drain region formed in the embedded epitaxial layer on each side of the gate structure; wherein the width of the gate structure is less than 20 nm; and the embedded epitaxial layer comprises a first epitaxial layer of SiAs, or the embedded epitaxial layer is formed by stacking a second epitaxial layer of SiAs and a third epitaxial layer of SiP. The present application can improve the carrier mobility of the device and improve the short channel effect.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Abstract: The present application provides a method for improving the metal work function boundary effect in FinFET process, the method comprises steps of: depositing a first TiN layer on four fin structures. The first TiN layer has no gap between the second and the third fin structures; removing the first TiN layer up to a first distance from the midline between the second and third fin structures at the second fin structure side; depositing a second TiN layer; removing the second and first TiN layers from second fin structure. The thickness of the TiN layer at the bottom edge of the fin structure at the later structure of the ultra-low threshold voltage P-type transistor will be smaller from this process. Thus formed TiN layer is less prone to a bottom undercut during etching, thereby reducing the metal boundary effect and increasing of the threshold voltage of the device.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: The present application discloses a self-aligned gate contact fin field effect transistor. A work function metal layer and a metal conductive material layer of a gate structure are etched back and a first top trench is formed in a top. The first top trench is filled with a first cap layer. A self-aligned gate contact metal zero layer formed in the first top trench is formed on a top of more than one fin intersecting with a gate metal strip. Sidewalls are formed on two sides of a gate trench. The sidewalls include an air sidewall. A source/drain contact metal zero layer spans each fin and is in a strip structure. Each source/drain contact metal zero layer is etched back and a second top trench is formed in a top. The second top trench is filled with a second cap layer.

Abstract: The present application discloses an integrated circuit structure of N-type and P-type fin transistors, wherein the N-type and P-type fin transistors are respectively formed on first and second fins, first and second diffusion breakdown structures are respectively provided on the first and second fins. A first dielectric layer of the first diffusion breakdown structure is made of a stress material to enable the first diffusion breakdown structure to have a first stress. A second dielectric layer of the second diffusion breakdown structure is made of a stress material to enable the second diffusion breakdown structure to have a second stress different from the first stress. The first stress is configured according to a requirement of improving carrier mobility of a first channel area, and the second stress is configured according to a requirement of improving carrier mobility of a second channel area.