Patents by Inventor Wenyong Deng

Wenyong Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Routing interconnect of integrated circuit designs with varying grid densities
    Patent number: 9177093
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 3, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS WITH VARYING GRID DENSITIES
    Publication number: 20140215426
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Interconnect routing methods of integrated circuit designs
    Patent number: 8386984
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS
    Publication number: 20130031524
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Routing interconnect of integrated circuit designs
    Patent number: 8365128
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: January 29, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation
    Patent number: 8291365
    Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: October 16, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Routing methods for integrated circuit designs
    Patent number: 8255857
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 28, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS
    Publication number: 20090113371
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 30, 2009
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • INTERCONNECT ROUTING METHODS OF INTEGRATED CIRCUIT DESIGNS
    Publication number: 20090113372
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 30, 2009
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS
    Publication number: 20090106728
    Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 23, 2009
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Methods of routing an integrated circuit design
    Publication number: 20060190897
    Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: January 6, 2006
    Publication date: August 24, 2006
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Method and apparatus for scalable interconnect solution
    Patent number: 7036101
    Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: April 25, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
  • Method and apparatus for scalable interconnect solution
    Publication number: 20020120912
    Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 29, 2002
    Inventors: Limin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao